• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.3
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• pp.81-86
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• 2010

Since CORDIC (COordinate Rotation DIgital Computer) is able to carry out the phase operation, such as vector to phase conversion or rotation of vectors, with adders and shifters, it is well suited for the design of the frequency synchronization unit in OFDM receivers. It is not easy, however, to fully utilize the CORDIC in the OFDM demodulator because of the non-linear characteristics of the direction sequence (DS), which is the representation of the phase in CORDIC. In this paper a new representation method is proposed to linearize the direction sequence approximately. The maximum phase error of the linearized binary direction sequence (LBDS) is also discussed. For the purpose of designing the hardware, the architectures for the binary DS (BDS) to LBDS converter and the LBDS to BDS inverse converter are illustrated. Adopting LBDS, the overall frequency synchronization hardware for OFDM receivers can be implemented fully utilizing CORDIC and general arithmetic operators, such as adders and multipliers, for the phase estimation, loop filtering of the frequency offset, derotation for the frequency offset correction. An example of the design of 22 bit LBDS for the T-DMB demodulator is also presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.30-38
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• 2012

This paper presents packet detection, frequency offset estimation architecture and performance analysis for OFDM-based wireless personal area network (WPAN) systems. Packet detection structure is used to find the start point of a packet exactly in WPAN system as the correlation value passes the constant threshold value. The applied autocorrelation structure of the algorithm can be implemented simply compared to conventional packet detection algorithms. The proposed frequency offset estimation architecture is designed for phase rotation process structure, internal bit reduction to reduce hardware size and the frequency offset adjustment block to reduce look-up table size unlike the conventional structure. If the received signal can be compensated by estimated frequency offset through the correction block, it can reduce the impact on the frequency offset. Through the performance result, the proposed structure has lower hardware complexity and gate count compared to the conventional structure. Thus, the proposed structure for OFDM-based WPAN systems can be applied to the initial synchronization process and high-speed low-power WPAN chips.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.11a
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• pp.91-94
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• 2009

현재 여러 나라에서 유럽의 위성 전송 시스템인 DVB-S 표준을 적용한 위성방송이 실시되고 있다. 또한 HDTV와 같은 광대역 방송 서비스, 인터넷 서비스 제공을 위한 효율적인 위성링크 등의 필요성으로 인해 2세대 위성방송 표준인 DVB-S2 (Digital Video Broadcasting via stellite) 표준이 제정되었다. DVB-S2 수신기의 반송파 동기부는 대부분의 상용 DVB-S2 수신기에 사용되는 상용 부품으로 인한 상당히 큰 초기 반송파 주파수 오차(심볼속도 대비 20%)를 정확하게 추정하고 복구해야만 한다. 이런 이유로, 기존의 DVB-S2 수신기의 반송파 주파수 복구부는 많은 연산량을 필요로 하고 복잡한 하드웨어 구조를 가진다. 이에 본 논문에서는 기존의 반송파 주파수 복구부에 비해 성능의 열화가 없고, 간단한 구조를 가지는 견고한 반송파 주파수 복구부 방식을 제안하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.218-230
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• 1993

A power line modem(PLM) which transfers data safely through power lines in houses or small offices is considered. When a power line is used for communications, transmitted signals could be affected by the channel characteristics such as frequency-selective fading, interference, and time-varying attenuation. In order to overcome these impairments, a direct sequence(DS) technique which is well known as an effective instrument against a variety of interferences and hostile channel properties is employed. Using a DS technique, however, requires more circuits such as PN code generator circuits, code modification circuits, and complicated synchronization circuits, and it also results in substantial acquisition delay. In this paper, some of these circuits are implemented via software programmed in the system controller, and the complicated synchronization circuits are replaced by simple circuits utilizing a 60 Hz power signal for synchronization. The synchronization ciruits used in this paper virtually eliminate the substantial acquisition delay, and is also designed to free influence of 60 Hz zero crossing jitters which reside in a power signal. As a result, a PLM using a DS technique is realized in the form of wall-socket plug, and the PLM hardware would be very much simplified.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.118-125
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• 2008

In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.807-813
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• 2009

A Satellite transponder is the Communication system to process signal with up-link signal recovery, and transmit to ground station through down-link. The orbit flight in the deep space causes high doppler shift in the received signals from the ground station so that the Carrier recovery and fast synchronization system are essential for the transponder system. The conventional analog transponder is employing the system's carrier recovery along with the PLL (Phase Locked Loop) designed for satellite's operation. This paper presents a digital carrier recovery scheme which can provide more reliable and software reconfigurable implementation technique for satellite transponder system without verifying scheme along with transponder designed for short distance or deep space satellite.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.34-41
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• 1998

In this paper, we evaluate synchronization techniques suitable for high-speed ATM satellite communications with a transmission rate of 155Mbit/s, and propose optimal algorithms that improve the tracking performance, where QPSK is selected for a modulation scheme, and the receiver is operated in burst mode. Based on these asumptions, we proposed modified algorithms and architectures for automatic frequency control(AFC), carrier recovery(CR), and symbol timing recovery(STR) for burst acquisition. Analysis is performed under AWGN environments with respect to the number of required symbol, steady-state stability, and hardware implementation for the proposed algorithms.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.476-482
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• 2014

Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. IEEE 802.15.4 LR-WPAN system using 2.45 GHz frequency band is very popular for the sensor applications. However, since LR-WPAN only supports the data rate of 250 kbps, it has a limit to be applied to various sensor networks. Therefore, we define the preamble structure which can support the data rates of 31.25 kbps, 62.5 kbps, 125 kbps, and present the low-complexity hardware architecture for time synchronizer based on double-correlation algorithm which can resist the CFO (carrier frequency offset). Implementation results show that the proposed time synchronizer include the logic slice of 18.36 K and four DSP48s, which are reduced at the rate of 79.1% and 99.4%, respectively, compared with existing architecture.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.49-56
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• 2006

This paper describes the design and the verification of IEEE 802.15.4 LR-WPAN 2.4GHz Physical layer for Ubiquitous Sensor Network(USN). We designed the Carrier Frequency Offset(CFO) compensation satisfied the frequency tolerance of IEEE 802.15.4 LR-WPAN and the adaptive matched filter that re-setting of the threshold for the symbol synchronization of the various USN environment. The multiplications is reduced 1/16 by this method each other at i, q phases and has 0.5dB performance improvement in detection probability. Proposed baseband system is designed with verilog HDL and implemented using FPGA prototype board.