• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.7
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• pp.885-890
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• 2020

In the distance measurement system the time-to-digital conversion circuit used measures the distance using the time interval between the start signal and the stop signal. The time interval is generally converted to digital information using a counter circuit considering the response speed. Therefore, a clock signal with a high frequency is required to improve precision, and a clock signal with a high frequency is also required to measure fine distances. In this paper, a counter circuit was designed to increase the accuracy of distance measurement while using the same frequency. The circuit design was performed using a 0.18㎛ CMOS process technology, and the operation of the designed circuit was confirmed through HSPICE simulation. As a result of the simulation, it is possible to obtain an improvement of four times the precision compared to the case of using a general counter circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.599-607
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• 2004

In this paper, using phase locked loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation fur modulation signal whose frequency covers from outside to inside of the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and of blocking the intereference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design. In addition, the novel measurement method of the wideband FM modulation index is suggested verified With the suggest measurement, it can be successfully shown the designed circuit has the expected frequency deviation.

• Journal of Advanced Navigation Technology
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• v.3 no.2
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• pp.120-131
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• 1999

For the phase measurement in the radar system using the magnetron pulse source, the STALO (Stable Local Oscillator) frequency need to be controlled to provide the stable intermediate frequency. In radar receiver, AFC(Automatic Frequency Control) circuit detects the transmitting frequency change and controls the STALO frequency to keep the intermediate frequency stable. In this paper, we designed and implimented AFC circuits for radar receiver. The frequency deviation is detected and compared with the reference frequency and the STALO frequency is controlled by the digital command signal.

• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 1998.04a
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• pp.220-225
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• 1998

레이다를 이용한 콘크리트 구조믈의 지진으로 인한 손상도를 파악하기 위해, 콘크리트의 전자기적 특성(dielectric properties)을 레이다 작용 주파수 대역인 200MHz에서 6GHz 영역까지 측정하였다. 이의 측정을 위해 실험실에서 콘크리트의 전자기적 특성 계측을 가능하게 하는 회로망분석기(network analyser)를 사용하였다. 콘크리트의 전자기적 특성은 open-ended coaxial probe를 회로망 분석기에 연결하여 측정하였고, 실험전 측정값을 보정(calibration)하는 기법을 찾아내었다. 주파수의 변화와 함께 콘크리트 시편안에 포함된 수분의 양을 조절함으로써, 실제 콘크리트 구조물이 가질 수 있는 상태를 시편을 통해 측정하였다. 측정결과는 콘크리트의 전자기적 특성이 주파수와 수분함량에 따라 변하는 것을 보여주었으며, 이는 레이다를 이용한 콘크리트 구조물의 지진 손상도 파악 방법 개발에 필요한 자료를 제공하였다.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1486-1487
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• 2008

MEMS 각속도계에서 일정한 크기와 주파수를 가지는 진동을 주기 위한 공진기 회로는 각속도계의 성능에 가장 큰 영향을 미친다. 특히 공진기 회로에서 기계구조물의 미세한 진동에 의해 발생되는 수 pico-coulomb의 전하를 증폭하는 전하증폭기와 feedback된 신호를 안정된 크기로 만들어 주는 AGC(Automatic Gain Control) 회로의 정밀도가 MEMS 각속도계의 정밀도를 결정짓는다. 본 논문에서는 전하증폭기의 실제적인 회로의 등가 회로 출력 공식을 실험을 통하여 확인하였고, 입력 신호의 주파수가 MEMS 각속도계의 설계 공진 주파수인 30kHz일 때 0.15 pC 단위까지 측정 가능함을 확인하였다. AGC회로의 경우 simulation을 통하여 동작을 확인하였고, 실제 AGC 회로를 제작하여 실험한 결과, 오실로스코프로 확인하기 어려울 정도로 안정된 출력을 얻었다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.12
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• pp.49-57
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• 2001

In this paper, equivalent circuit model and novel model parameter extraction method of a silicon(Si) substrate are presented. Substrate coupling through Si-substrate is quantitatively investigated by analyzing equivalent circuit with operating frequency and characteristic frequencies (i.e., pole and zero frequency) of a system. For the experimental verification of the equivalent circuit and parameter extraction method, test patterns are designed and fabricated in standard CMOS technology with various isolation distances, substrate resistivity, and guard-ring structures. Then, these are measured in l00MHz-20GHz frequency range by using vector network analyzer. It is shown that the equivalent-circuit-based HSPICE simulation results using extracted parameters have excellent agreement with the experimental results. Thus, the proposed equivalent circuit and parameter extraction methodology can be usefully employed in mixed-signal circuit design and verification of a circuit performance.

• Proceedings of the KAIS Fall Conference
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• 2002.11a
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• pp.197-200
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• 2002

본 논문에서는 IMT-2000용 AB급 대전력 증폭기를 설계 및 제작하였다. 전력증폭기의 주파수 대역은 IMT-2000용 순방향 주파수인 2110MHz-2170MHz에서 AB급으로 동작하도록 하였고, 고효율성과 우수한 선형성 소자인 LDMOSFET를 사용하였다. 설계 특성에 맞는 최적부하를 찾아 마이크로 스트립 회로로 입력 및 출력 정합 회로를 구현하였다 임피던스 정합 방법으로는 소자를 실제 측정상태에서 입력단과 출력단에 튜너를 삽입하고 기본 주파수에서 최대 출력상태를 만족하는 임피던스를 튜너로 구현한 후, 튜너를 제거하고 튜너의 입력 임피던스를 Network Analyzer로 측정하여 최적 부하 임피던스를 추출하는 로드풀 방법을 사용하였다. 대전력 증폭기의 측정결과로는 2-톤 인가시 40.57dBm의 출력결과를 얻을 수 있었고 30.61dBc의 상호 혼변조 특성을 확인하였으며, 원신호의 하모닉(Hamonic) 주파수 성분과는 21.46dBc의 차이를 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.44-44
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• 2001

본 논문에서는 CMOS로 구현된 3.3V 8-bit 200MSPS의 Folding / Interpolation 구조의 A/D 변환기를 제안한다. 회로에 사용된 구조는 FR(Folding Rate)이 8, NFB(Number of Folding Block)가 4, Interpolation rate 이 8이며, 분산 Track and Hold 구조를 회로를 사용하여 Sampling시 입력주파수를 Hold하여 높은 SNDR을 얻을 수 있었다. 고속동작과 저 전력 기능을 위하여 향상된 래치와 디지털 Encoder를 제안하였고 지연시간 보정을 위한 회로도 제안하였다. 제안된 ADC는 0.35㎛, 2-Poly, 3-Metal, n-well CMOS 공정을 사용하여 제작되었으며, 유효 칩 면적은 1070㎛×650㎛ 이고, 3.3V전압에서 230mW의 전력소모를 나타내었다. 입력 주파수 10MHz, 샘플링 주파수 200MHz에서의 INL과 DNL은 ±1LSB 이내로 측정되었으며, SNDR은 43㏈로 측정되었다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.44-54
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• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

• Journal of the Korea Convergence Society
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• v.9 no.2
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• pp.1-6
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• 2018

In this study, the investigation results of conducted and radiated emission for DC/DC converter circuit applied in electric vehicles are presented. A frequency spreading circuit was used to improve the EMI characteristics of a power converter designed by using MPQ4433 chip. The frequency spreading circuit using a TLV3201 chip was designed and applied to the power converter. A PCB was fabricated based on the EMI minimization procedures and simulated and measured results were presented for the far-field and near-field conducted and radiated emissions using the fabricated circuit. The measurement were done as CISPR 25 standardized test procedures. It is clearly showed that the EMI characteristics were improved 20% in case frequency spreading was applied. The EMI reduction technique using the frequency spreading proposed in this study was first applied to the design of power converter module for automobile. It is expected that the method presented here can be effectively used for EMI improvement in the future.