• Proceedings of the Korean Information Science Society Conference
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• 2006.10b
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• pp.408-411
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• 2006

유비쿼터스 컴퓨팅 환경에서 서비스를 제공함에 있어 지능적인 수행 능력은 사용자의 만족도를 높여주는 핵심 요소이다. 시스템의 지능을 부여하기 위해서는 지식을 관리, 처리, 활용하는 기능이 필요한데, 이들 기능은 그 지식이 어떻게 표현되어 있는지에 큰 영향을 받는다. 일차 술어 논리 기반 지식 표현 방법은 폭넓은 표현 범위와 유연한 지식 정의, 추론 방법으로 선호되고 있지만, 복잡한 계산 비용을 갖고 있기 때문에, 전문적인 지식 처리 시스템이 아닌 경우, 불필요한 계산 비용이 소요된다. Description Logic은 Frame기반 지식 표현 방식으로 일차 술어 논리를 사용하는 것보다 지식을 표현할 수 있는 범위는 제한적이지만, 빠른 추론 결과를 보장해 준다. 유비쿼터스 컴퓨팅 환경에서는 분산된 다양한 오브젝트들이 협력과정을 통해 사용자에게 지능적인 서비스를 제공하게 되고, 이들 개별적인 오브젝트들은 저사양의 계산능력을 갖고 있다고 가정된다. 그러므로, 저사양의 컴퓨팅 오브젝트들을 조합하여 지능적인 서비스를 성공적으로 제공하기 위해서, 각각의 오브젝트들은 제한된 지식을 효과적으로 관리할 수 있는 방법이 필요하다. 이를 위해 본 논문에서는 Frame 기반의 Description Logic을 기반으로 SUNHI의 표현 범위를 가진 인식론적 온톨로지 표현 언어를 제안하고, SUNHI의 표현 범위의 효율성을 증명하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1477-1486
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• 2000

This paper proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit design.. The proposed algorithm decreases the power consumption by partitioning a given circuit utilizing a kernel, and reduces the area overhead by minimizing duplicated gates in the partitioned subcircuits. Experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating circuits consuming 43.6% less power with 30.7% less area on the average, when compared to the previous algorithm based on precomputation circuit structure.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.209-212
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• 2000

This paper describes the design and implementation of a hard- wired AGV controller using CPLD(Complex Programmable Logic Device). The proposed controller manages a guidance equipment, motor and I/O sequence controller for a self-control traveling. Compared with a conventional $\mu$-processor, the CPLD controller using a hard-wired control method can reduce a difficult programming process. Also, the total costs of production are reduced, such as development time, product's size and difficulty because memory, combinational logic and sequential logics are implemented by CPLD. The Controller designed using behavioral description method with VHDL and was synthesized by MAX＋Plus II of the ALTERA co. We implemented controller using EPF10K10LC84-4 device.

• Journal of KIISE:Software and Applications
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• v.30 no.7_8
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• pp.642-648
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• 2003

In this paper, we are interested in checking equivalence of FSMs(finite state machines). Two FSMs are equivalent if and only if their responses are always equal with each other with respect to the same external stimuli. Equivalence checking FSMs makes complicated FSM be substituted for simpler one, if they are equivalent. We can also determine the system satisfies the requirements, if they are all written in FSMs. In this paper, we regard equivalence checking problem as model checking one. For doing so, we construct the product model $M ={M_A} {\beta}{M_B} from two FSMs ${M_A} and {M_B}$. And we also get the temporal logic formula ${\Phi}$ from the equivalence checking definition. Then, we can check with model checker whether if satisfies ${\Phi}$, written $M= {.\Phi}$. Two FSMs are equivalent, if $M= {.\Phi}$ Otherwise, it is not equivalent. In that case, model checker generates counterexamples which explain why FSMs are not equivalent. In summary, we solve the equivalence checking problem with model checking techniques. As a result of applying to several examples, we have many satisfiable results.

• Korean journal of communication and information
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• v.29
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• pp.147-188
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• 2005

This study attempts to review and evaluate the sociological engagement and media practices of an eminent French sociologist Pierre Bourdieu. In the first part of the paper, I presented some characteristics of Bourdieu's view on the sociological engagement. In the second part, I also examined Bourdieu's alternative media strategies(ARSS, Liber, Raisons d'agir) which were designed to intervene effectively in the academy and public sphere of French society. For Bourdieu, the sociological engagement can be conceived and legitimized as follows: first, the talents of the ensemble of 'specific intellectuals' in Foucaldian sense should be combined to constitute a kind of 'large collective of intellectuals' Second, this 'collective of intellectuals' should make 'corporatist' efforts to improve the autonomy of the 'field of cultural production', which is the indispensable condition for the conquest of 'the universal' Bourdieu tried to realize his logic of sociological engagement through all his intellectual works, media activities and political intervention. In appreciating positively the consistency and originality of Bourdieu's theory and practice of engagement, I proposed to reconsider some limits of his 'modern' politics - enlightenment, science, collectivity - in today's 'postmodern condition'.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.6
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• pp.55-62
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• 2005

It is essential for a fuzzy logic controller to have an appropriate set of rules to perform at the desired level. The linguistic structure of the fuzzy logic controller allows a tentative linguistic policy to be used as an initial rule base. At the design stage, if one can reasonably assemble a good collection of rules, it may then be possible to be tuned to improve the controller performance. In this paper, we proposed the shifting method of rule base table to improve the performance of fuzzy controller. The proposed method is based on the principle of that the effect of the output to regulate the system would be greater when the error increases and the effect of output would be less when the error decreases. According to simulation results, it is an effective method to improve the fuzzy control rule base and the performance of fuzzy logic controllers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.56-64
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• 2007

We developed the first automatic design system targeting a promising hybrid CMOS-Nanoelectronics Architecture called CMOL. The CMOL architecture uses NOR gates to implement combinational logic. In this hybrid CMOS-nanoelectronics architecture, logical functions and the interconnections share the nanoelectronics hardware resource. Towards automating the CMOL physical design process, we developed a model for the CMOL architecture, formulated the placement and routing problems for the CMOL architecture subject to the unique CMOL specific constraints, and solved it by combining a placement algorithm with a gate assignment algorithm in a loop. We validated the proposed approach by implementing several industrial strength designs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.439-447
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• 2000

현재 방범 시스템은 적외선, 초음파 둥의 I-지기의 신호에 의존하여 외부로부터의 침입을 감지하고 있으나 방범 시스템이 설치된 환경에 따라 이런 감지기의 정확성이 달라지므로 오 동작의 가능성을 포함하며 신뢰성이 저하되고 있다. 실제 외부로부터의 침입을 확인하기 위해서는 화상과 음성 그리고 감지기의 신호를 조합하여 정확한 판단이 가능하지만 화상을 전송하기 위해서는 고가의 회선비용을 부담해야만 한다. 하지만 인터넷을 이용하여 화상을 전송하는 제품들이 출시되면서 Real-time 화상감시가 가능해졌다. 이런 화상감시 제품들은 Netscape, MS Explorer와 같은 표준 Web Browser을 통해 Real-time으르 전세계 어디서나 화상을 감시할 수 있다는 장점을 가지고 있다. 적용분야는 호텔주변, 관광지의 여러 명소에 설치 후 홈페이지에 링크시켜 홍보용으로 사용하거나 공장 주요시설, 교통상황 둥의 중요지역의 Monitoring에 활용하고 있다. 그러나 방범 시스템에 적용하기에는 감지기의 확장성, 방범 관제센터 시스템과의 연동이 부족하여 본 고에서는 현재 출시된 화상감시 시스템과 기존 방범시스템을 Integration하여 방범의 최종 목표인 화상과 감지기 신호의 조합에 따른 정확한 방범시스템의 구현에 대해서 기술하고자 한다. 화상방범시스템의 구현은 크게 두 가지로 나누어지며 첫째는 화상감시 시스템과 방범시스템간의 통신을 설계하는 것으로 기존 대부분의 방범시스템이 사용하는 RS-485 통신 프로토콜을 재설계하여 화상감시 시스템과의 통신을 설계하였으며 둘째는 화상감시시스템과 관제센터 시스템간의 통신을 설계하는 것으로 현재 화상감시 시스템의 TCP/IP 프로토콜을 이용한 socket 통신으로 관제센터 시스템과의 실시간 데이터 전송을 가능하게 했다. 이 시스템을 활용할 경우 고객들은 반드시 관제센터시스템의 인증을 거쳐야 하므로 고객의 DataBase를 축적할수 있으며 이 정보를 활용하여 인터넷 화상방범 서비스 Potal Site구축이 가능하다는 장점이 있다.

• Journal of KIISE:Software and Applications
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• v.29 no.5
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• pp.289-294
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• 2002

It is known that restructuring feed-forward neural network affects generalization capability and efficiency of the network. In this paper, we introduce a new approach to restructure a neural network using abstraction of the hidden knowledge that the network has teamed. This method involves extracting local rules from non-input nodes and aggregation of the rules into global rule base. The extracted local rules are used for pruning unnecessary connections of local nodes and the aggregation eliminates any possible redundancies arid inconsistencies among local rule-based structures. Final network is generated by the global rule-based structure. Complexity of the final network is much reduced, compared to a fully-connected neural network and generalization capability is improved. Empirical results are also shown.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.