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Image Measurement and Processing using Near-Range Passive Millimeter-wave Imaging System (근거리 수동 밀리미터파 이미징 시스템을 이용한 영상 측정과 영상처리)

  • Jung, Kyung Kwon;Yoon, Jin-Seob;Chae, Yeon-Sik
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.8
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    • pp.159-165
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    • 2015
  • In this paper, we designed and tested of the passive millimeter-wave imaging system in near range. The proposed passive millimeter-wave imaging system consists two parts. The first part is a 94 GHz band millimeter imaging sensor which is coupled to an antenna, two LNAs, and a diode detector. The second part is a control unit. The control unit is consists of the 2-axes Cartesian robot, the data acquisition (DAQ), and imaging program. The 2-axes Cartesian robot should be able to scan a 2-D image of the metalic tools, IC card and plastic objects, with a raster scanning method. The passive millimeter-wave image of $20{\times}20$ pixels is acquired within less than 60s, and is immediately displayed and stored for post processing.In order to improve the image quality, interpolation methods are applied.

Implementation of UHF RFID Tag Emulator (UHF 대역의 RFID 태그 에뮬레이터 구현)

  • Park, Kyung-Chang;Kim, Hanbyeori;Lee, Sang-Jin;Kim, Seung-Youl;Park, Rae-Hyeon;Kim, Yong-Dae;You, Young-Gap
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.11
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    • pp.12-17
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    • 2009
  • This paper presents a tag emulator for a UHF band RFID system. The tag emulator supports the 1800-6C and EPC global class 1 generation 2 standards. The transmitted signal from a reader is generated using the PIE coding and ASK modulation methods. Signals of a tag are from the FM0 coding and ASK modulation methods. The ARM7 processor carries out the overall control of the system and signal analysis of incoming data. The verification of the tag emulator employs the application platform implemented in C++. Users can define parameter values for protocol during the application run. The tag emulator presented in this paper allows evaluating various design alternatives of the target RFID system in real applications.

A Study on Metal Surface Thickness Detection Using Indsctive Proximity Sensor (유도성 근접센서를 통한 금속표면 두께 검출에 관한 연구)

  • Park, Hwa-Beom;Lee, Seung-Jae;Kim, Young-Kil
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.10a
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    • pp.231-234
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    • 2007
  • The magnetic sensor using electromagnetic principle. which transfers magnatic into electric. is the electric component.It has been widely applied to the industry, university and the reseach. However there are some problems. Not only the korean domestic sensor manufacture skills are still lower then the advanced manufacture's but also production of sensor is not well organized yet. Due to cahnging excitation cvurrent, excitation freq and the rate magnetic permeability core, there sometimes would be distorted phenomena or loaded phenomena which result in limited measurment range. Therefore, the signal conversion device should support to receive undistorted and nice output. This paper focuses on both the design of signal transform circuit using inductive proximity sensor and the signal transfer equipment (Z device) which detects thickness of painted material.

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Design and Evaluation of a Fuzzy Logic-based Selective Paging Method for Wireless Mobile Networks (무선 이동망을 위한 퍼지 논리 기반 선택적 페이징 방법의 설계 및 평가)

  • 배인한
    • Journal of KIISE:Information Networking
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    • v.31 no.3
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    • pp.289-297
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    • 2004
  • State-of-the-art wireless communication networks allow dynamic relocation of mobile terminals. A location management mechanism is required to keep track of a mobile terminal for delivering incoming calls. In this paper, we propose a fuzzy logic-based selective paging method to reduce paging cost. In the proposed fuzzy logic-based location management method, the location update uses the area-based method that uses direction-based together with movement-based methods, and the location search uses the fuzzy logic-based selective paging method based on the mobility information of mobile terminals. A partial candidate paging area is selected by fuzzy control rules, then the fuzzy logic-based selective paging method pages only the cells within the partial candidate paging area. The performance of proposed fuzzy logic-based location management method is to be evaluated by both an analytical model and a simulation, and is compared with those of LA and BVP methods. From these evaluation results, we know that the proposed fuzzy logic-based location management method provide better performance than other location management methods.

Design of a Hybrid Data Value Predictor with Dynamic Classification Capability in Superscalar Processors (슈퍼스칼라 프로세서에서 동적 분류 능력을 갖는 혼합형 데이타 값 예측기의 설계)

  • Park, Hee-Ryong;Lee, Sang-Jeong
    • Journal of KIISE:Computer Systems and Theory
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    • v.27 no.8
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    • pp.741-751
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    • 2000
  • To achieve high performance by exploiting instruction level parallelism aggressively in superscalar processors, it is necessary to overcome the limitation imposed by control dependences and data dependences which prevent instructions from executing parallel. Value prediction is a technique that breaks data dependences by predicting the outcome of an instruction and executes speculatively its data dependent instruction based on the predicted outcome. In this paper, a hybrid value prediction scheme with dynamic classification mechanism is proposed. We design a hybrid predictor by combining the last predictor, a stride predictor and a two-level predictor. The choice of a predictor for each instruction is determined by a dynamic classification mechanism. This makes each predictor utilized more efficiently than the hybrid predictor without dynamic classification mechanism. To show performance improvements of our scheme, we simulate the SPECint95 benchmark set by using execution-driven simulator. The results show that our scheme effect reduce of 45% hardware cost and 16% prediction accuracy improvements comparing with the conventional hybrid prediction scheme and two-level value prediction scheme.

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Implementation of Digital Desoldering System for Removing Lead-free Solder (무연 솔더 제거를 위한 디지털 디솔더링 시스템 구현)

  • Oh, Kab-Suk
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.1
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    • pp.322-328
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    • 2012
  • This paper deals with a digital Desoldering system for removing lead-free solder. We proposed a Desoldering system that is to cope with the changed work environment of the solder materials changing from lead solder to lead-free solder, we can be quickly stable to the set temperature, and continuous operation is possible. Proposed system consists of a Desoldering station and a Desoldering gun. For the PID temperature control, we designed the 8bit MCU peripheral circuit. We had a few experiments to confirm the performance of the proposed system, and compared with the specification of same kind of imports. As a result, proposed system than the imported products showed good performance as follows: the time to reach operating temperature is 11 seconds faster, ripple temperature variation is $1.5^{\circ}C$ lower, temperature recovery rate is about $0.14^{\circ}C$/sec faster.

An Implementation of Real-Time SONAR Signal Display System using the FPGA Embedded Processor System (FPGA 임베디드 프로세서 시스템을 사용한 실시간 SONAR 선호 디스플레이 시스템의 구현)

  • Kim, Dong-Jin;Kim, Dae-Woong;Park, Young-Seak
    • Journal of the Institute of Convergence Signal Processing
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    • v.12 no.4
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    • pp.315-321
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    • 2011
  • The CRT monitor display system for SONAR signal that are commonly used in ships or naval vessels uses vector scanning method. Therefore the processing circuits of the system is complex. Also because production had been shut down, the supply of parts is difficult as well as high-cost. FPGA -based embedded processor system is flexible to adapting to various applications because it makes simple processing circuits and its core is easily reconfigurable, and provides high speed performance in low-cost. In this paper, we describe an implementation of SONAR signal LCD display system using the FPGA embedded processor system to overcome some weakness of existing CRT system. By changing X-Y Deflection and CRT control blocks of current system into FPGA embedded processor system, our system provides the simplicity, flexibility and low-cost of system configuration, and also real-time acquisition and display of SONAR signal.

Design and Implementation of a Distributed Object Programming Language supporting Peer Replicated Object Model (대등관계 복제객체 모델을 지원하는 분산 객체 프로그래밍 언어의 설계 및 구현)

  • Sin, Beom-Ju;Lee, Dong-Hyeon
    • Journal of KIISE:Computing Practices and Letters
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    • v.5 no.4
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    • pp.449-456
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    • 1999
  • 본 논문은 C++에 분산 객체 프로그래밍 기능을 추가한 D++ 언어를 제안한다. 대등관계 복제객체 모델을 지원하는 D++는 분산 클래스의 정의, 멤버 함수의 일치성 제어 정의 기능, 그리고 영구 객체 이름에 기반한 분산 객체를 정의할 수 있는 언어 구조를 제공한다. D++ 프로그램에서 새로이 생성되는 분산 객체는 생성 시에 제공되는 객체의 영구 이름과 동일한 영구 이름을 갖는 분산 객체가 존재할 경우 해당 객체들과 복제 관계를 유지함으로써 정보를 공유한다. 각 복제 객체들은 서로 간에 대등한 관계를 가지며, 멤버 함수 정의 시에 기술되는 특성에 따라 일치성이 유지된다. 이 같은 D++의 분산 객체 모델은 실시간 그룹웨어의 기본 요구 사항인 분산 환경에서의 정보 공유 및 사건 공지 기능을 자연스럽게 해결해 주기 때문에 실시간 그룹웨어의 개발을 효율적으로 지원할 수 있을 것으로 기대한다. Abstract This paper proposes D++ programming language that is an extension of C++ for distributed object oriented programming. The D++, which supports peer-to-peer object model, provides new language constructs for the definition of distributed classes, the definition of the consistency control of the member function and the definition of distributed object variables with the persistent name. In D++, when the persistent name of a newly created distributed object is same as that of an existing distributed object, the new distributed object replicates object state of the existing distributed object and thus they share the object state. The replicas have peer relation and the consistency among them is maintained according to the characteristic described on the definition of designated member functions. It is expected that D++ language increases efficiency in development of real-time groupware because the distributed object model of D++ naturally supports the information sharing and event notification that are the basic functions required when building real-time groupware.

Tunable bragg filter of $Si_3N_4-SiO_2$ waveguide using thermooptic effect (열광학 효과를 이용한 $Si_3N_4-SiO_2$ 도파로 가변 브래그필터)

  • 이형종;정환재
    • Korean Journal of Optics and Photonics
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    • v.3 no.4
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    • pp.244-251
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    • 1992
  • Buried Bragg filters of single mode $Si_{3}N_{4}$ rib waveguide with a cover layer of $SiO_{2}$ and grating at the interface of $Si_{3}N_{4}$ and $SiO_{2}$ are designed and fabricated. Etching of the grating on $Si_{3}N_{4}$ waveguide core by buffered HF showed uniform etching with good control up to 1 nm. This buried type of Bragg filters are immune to contamination of the surface of device. The mode index and bandwidth of filters are determined by measurements of the transmission spectrum of Bragg filters and compared with that of calculation. Waveguide Bragg filters loaded with the micro-heater of Cr film and the cladding of silicone rubber are made to control the Brag wavelength of the filter. As a result the filter wavelength of the device moved by 0.41 nm for 10 mA current to the shorter side of wavelength proportional to the square of the current.

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A High Speed CMOS Arrayed Optical Transmitter for WPON Applications (WPON 응용을 위한 고속 CMOS어레이 광트랜스미터)

  • Yang, Choong-Reol;Lee, Sang-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38B no.6
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    • pp.427-434
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    • 2013
  • In this paper, the design and layout of a 2.5 Gbps arrayed VCSEL driver for optical transceiver having arrayed multi-channel of integrating module is confirmed. In this paper, a 4 channel 2.5 Gbps VCSEL (vertical cavity surface emitting laser) driver array with automatic optical power control is implemented using $0.18{\mu}m$ CMOS process technology that drives a $1550{\mu}m$ high speed VCSEL used in optical transceiver. To enhance the bandwidth of the optical transmitter, active feedback amplifier with negative capacitance compensation is exploited. We report a distinct improvement in bandwidth, voltage gain and operation stability at 2.5Gbps data rate in comparison with existing topology. The 4-CH chip consumes only 140 mW of DC power at a single 1.8V supply under the maximum modulation and bias currents, and occupies the die area of $850{\mu}m{\times}1,690{\mu}m$ excluding bonding pads.