• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.389-392
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• 2000

본 연구에서는 1, 2단자쌍 회로망의 임피던스 정합회로를 간단하고 빠르게 구할 수 있는 방안을 개발하였다. 우선 회로망의 전체 전달함수를 F 행열로 부터 계산하고, 이를 이용하여 양단의 부하저항 및 정합회로가 포함된 각각의 단자의 입출력 임피던스를 구하였으며, 이 식으로부터 정합용 소자의 정확한 값을 계산하였다. 본 연구의 타당성을 검증하기 위해 CDMA용 소자로 널리 사용되는 중간주파수 대역 withdrawal 가중형 SAW 필터에 본 연구의 결과를 적용하여 임피던스 정합 전후의 특성변화를 시뮬레이션과 실험을 통하여 동시에 확인하였다 그 결과 85.38 MHz의 중심주파수에서 비대역폭이 $1.2\%$, 삽입손실이 29dB, VSWR이 80인 필터를 본 연구방법을 이용하여 정합 한 경우, 각각 $1.8\%$, 9dB, 3으로 향상됨을 시뮬레이션과 실험을 통해 확인하였다. 본 연구결과는 SAW 디바이스의 정합에 매우 용이하게 이용될 수 있을 뿐만 아니라 일반적인 1, 2단자쌍 회로망의 임피던스 정합에도 널리 사용될 수 있다

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.69-72
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• 2000

본 논문에서는 비선형 확장 칼만 필터(Nonlinear Extended Kalman Filter)를 이용한 강인한 스테레오 정합 알고리즘을 제안한다. 기존의 스테레오 정합 알고리즘은 변이를 구할 때 좌, 우 영상을 화소별로 비교하여 검색영역을 모두 검색하였으나 제안된 알고리즘은 비선형 확장 칼만 필터를 통해 변이를 예측하고, 예측된 변이에 대한 좌, 우 영상값을 비교하는 과정을 반복적으로 수행함으로써 단지 몇 번의 검색을 통해 변이를 구하게 된다. 그리고, 양선형 보간법(bilinear interpolation)을 이용해 주위 화소들의 영향을 고려하여 예측된 변이에 대한 좌, 우 영상값을 비교함으로써 강인한 스테레오 정합의 결과를 얻을 수 있다. 제안된 알고리즘을 수행한 결과 본 알고리즘이 우수한 정합 성능을 가짐을 알 수 있었다.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.145-151
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• 2004

For wide-band spread spectrum communication systems such as IMT-2000, a digital matched filter is a key device for rapid spreading code synchronization. Although a digital matched filter can be implemented easily, large power consumption at the higher chip rate and large summation delay of longer chip length are the bottleneck of practical use. In this paper, we propose a optimized partial correlation digital matched filter structure which can be constructed of the so-called generalized hierarchical Golay sequence. a partial correlation structure can reduce the number of correlators, but enlarge the size of flip-flops. In this paper, The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. A proposed digital matched filter reduce the size of flip-flops by rounding method. and it reduces about 45 percentages of power dissipation and chip area as compared with digital matched filter which is not rounded. rounding. The proposed architecture was verified by using Xilinx FPGA.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.10
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• pp.8-13
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• 2009

The MF(matched filter) is the optimum signal detector that maximizes the output instantaneous signal power to average noise power ratio in white noise environment. But it cannot give the optimum detection performance if the background noise is not white. So, the whitening process preceding the matched filter is needed in the conventional detector which results in a PWMF(pre-whitening matched filter). Its performance is mainly affected by the estimation accuracy of non-white noise model which is used in the whitening procedure. To estimate more accurate model to improve performance, the computational complexity is increased. Therefore, a spectrum based detector which shows better performance than the PWMF under the similar complexity condition or less complexity under the similar performance condition is proposed in this paper. And its performance and complexity are analyzed and compared with the conventional PWMF.

• The Journal of the Acoustical Society of Korea
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• v.33 no.4
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• pp.262-267
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• 2014

Recently, long pulses are transmitted for target detection in active sonar application. Matched filtering implemented by simple convolution algorithm, requires massive computational power for long replica. The computational loads are reduced significantly by implementing the convolution in the frequency domain with overlap add method, but the performance degrades for specified input/output system delay which constrains the size of FFT function. For performance improvement, the replica could be partitioned into uniform blocks (FDL) by re-using IFFT operations, or variable blocks of increasing length (MC) by using the largest possible blocks to calculate the convolution. In this paper, by combining the strong points of the two methods, we propose a new filter partition structure that allows for further optimization of the previous two methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.99-106
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• 2004

In this Paper, the matched filter for searching initial synchronization in DSSS (direct sequence spread spectrum) receiver is studied. The matched filter with a single data flow path is described which can be presented by HDL (Hardware Description Language). In order to improve the processing time of operations for the filter, equations are arranged to represent two data flow paths and the associated hardware model is proposed. The model has an architecture based on parallelism and pipeline for fast processing, in which two data flow paths with a series of memory, multiplier and accumulator are placed in parallel. The performance of the model is analyzed and compared with the matched filter with a single data flow path.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.3
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• pp.76-79
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• 2014

Face recognition is very challenging because of the unexpected changes of pose, expression, and illumination. Facial detection in the mobile environments has additional difficulty since the computational resources are very limited. This paper discusses face detection based on frequency domain matched filtering in the mobile environments. Face detection is performed by a linear or phase-only matched filter and sequential verification stages. The candidate window regions are selected by a number of peaks of the matched filtering outputs. The sequential stages comprise a skin-color test and an edge mask filtering tests, which aim to remove false alarms among selected candidate windows. The algorithms are built with JAVA language on the mobile device operated by the Android platform. The simulation and experimental results show that real-time face detection can be performed successfully in the mobile environments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.203-206
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• 2008

기존의 대표적인 디지털 통신방식으로 주파수 편이 변조(FSK: frequency shift keying), 위상 편이 변조(PSK: phase shift keying), 진폭 편이 변조(ASK: amplitude shift keying) 방식들이 있다. 본 논문에서는 2진 정합필터를 이용하여 웨이브릿 편이변조 신호를 복원하는 알고리즘을 제안한다. 웨이브릿 편이 변조 시스템은 스케일링 함수(scaling function)와 웨이브릿(wavelet)을 이용한다. 스케일링 함수를 1로, 웨이브릿 함수를 0으로 할당하여 2진 데이터를 변조한다. 기존의 웨이브릿 편이 변조 시스템에서는 복원을 위해 후처리가 필요하였다. 된 논문에서는 2진정합필터를 이용하여 복원하므로, 별도의 후처리 과정 없이 복원을 가능하게 하였다. 모의실험 결과 제안한 알고리즘이 타당함을 확인하였다.

• The Journal of the Acoustical Society of Korea
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• v.22 no.2
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• pp.153-161
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• 2003

In this paper, we propose a wavelet-based detection method to identify efficiently the time-delay or multipath channel of ocean acoustic signals due to complex ocean medium and boundary layers. Our proposed method employs wavelet packet transform to analyze the received broadband acoustic signals and applies the matched filter to determine the time region of interest. Also, we present numerical testing that results on both the simulated and real data revealed the efficiency of this method in time-delay estimation and moreover its capability in estimating the time-delay of individual path in multipath channel, in which the arrival patterns are too close to be separated by the matched filter method.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.24-31
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• 2010

A receiver architecture with low complexity for chirp spread spectrum (CSS) of IEEE 802.15.4a is proposed. To demodulate the received signal at the highest signal to noise power ratio, matched filter is generally adopted for the receiver of wireless communication systems. It is, however, not resonable to adjust the matched filter to the receiver of CSS whose objectives are low complexity, low cost and low power consumption since complexity of the matched filter is high. In this paper, we propose a new receiver architecture using differential multiplication and accumulator not matched filter for demodulation. Also, bi-orthogonal decoder implemented by only adder/subtractor is proposed. The hardware resources for implementation are reduced in the proposed receiver architecture, although bit error rate performance is low compared with the receiver architecture based on the matched filter.