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Bae, Chang-Hyun;Yoo, Changsik
- Journal of the Institute of Electronics and Information Engineers
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- v.51 no.1
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- pp.97-103
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- 2014
In this paper, a clock-data recovery using a 1/8-rate phase detector is proposed. The use of a conventional full or half-rate phase detector requires relatively higher frequency of a recovered clock, which is a burden on the design of a sampling circuit and a VCO. In this paper, a 1/8-rate phase detector is used to lower the frequency of the recovered clock and a linear equalizer is used as a input circuit of a phase detector to reduce the jitter of the recovered clock. A test chip fabricated in a 0.13-${\mu}m$ CMOS process is measured at 1.5-GHz for a 3-Gb/s PRBS input and 1.2-V power supply.
https://doi.org/10.5573/ieie.2014.51.1.097 인용 PDF KSCI

An, Taek-Joon;Kong, In-Seok;Im, Sang-Soon;Kang, Jin-Ku
- Journal of IKEEE
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- v.17 no.4
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- pp.544-549
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- 2013
This paper describes a modified binary phase detector (Bang-Bang phase detector - BBPD) for jitter reduction in clock and data recovery (CDR) circuits. The proposed PD reduces ripples in the VCO control voltage resulting in reduced jitter for CDR circuits. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and verified using Dongbu $0.13{\mu}m$ CMOS technology. Simulation shows the CDR with proposed PD recovers data with peak-to-peak jitter of 10.96ps, rms jitter of 0.86ps, and consumes 16.9mW.
https://doi.org/10.7471/ikeee.2013.17.4.544 인용 PDF KSCI

Lee K. O.;So J. H.;Jung Y. S.;Yu G. J.;Choi J. Y.;Jung S. G.
- Proceedings of the KIPE Conference
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- 2004.07b
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- pp.494-497
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- 2004
계통연계형 태양광발전 시스템의 확대보급에 따라 단독운전 검출기법의 검출 성능에 대한 검증의 필요성이 대두되고 있다. 본 논문에서는 단독운전 검출기법의 대표적인 능동적 검출기법인 무효전력 변동기법 (reactive power variation method)과 주파수 쉬프트기법(active frequency drift method)을 IEEE Std 929-2000에서 명시된 단독운전검출 시험 방법을 이용하여 단독운전검출기법의 성능 및 불검출 영역(non-detection zone)에 대하여 비교 분석하였다.
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