• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.68-75
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• 2007

A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply which has dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna. The analog front end circuit of the proposed NFC transceiver consists of a transmitter and receiver of reader/writer block supporting NFC initiator or RFID reader mode, and a tag circuit for target of passive NFC mode or RFID tag mode. The maximum baud rate of the proposed NFC device is 212kbps by using UART serial interface. The chip has been designed and fabricated using a Magnachip's $0.35{\mu}m$ double poly 4-metal CMOS process, and the effective area of the chip is 2200um by 3600um.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.4 s.310
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• pp.53-59
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• 2006

This paper describes the new design technique of full wave rectifier (FWR) for precise measurement instrument and the chip implementation of this FWR circuit with measurement results. Conventional circuits have some problems of complex design and limited output range( $VDD/2{\sim}VLIIV1IT+$). Proposed FWR circuit was simply designed with two 2x1 MUXs, one high speed comparator, and one differential difference amplifier(DDA). One rail-to-rail differential difference amplifier(DDA) performs the DC level shifting to VSS and 2X amplification simultaneously, and enables the full range ($Vss{\sim}VDD$) operation. The proposed FWR circuits shows more than 50% reduction of chip area and power consumption compared to conventional one. Proposed circuit was implemented with 0.35um 1-poly 2-metal CMOS process. Core size is $150um{\times}450um$ and power dissipation is 840uW with 3.3V single supply.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.159-164
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• 2016

A wireless communication system is required to be implemented with the low power circuits because it uses a battery having a limited energy. Therefore, the current mode circuit has been studied because it consumes constant power regardless of the frequency change. However, the clock-feedthrough problem is happened by leak of stored energy in memory operation. In this paper, we suggest the current memory circuit to minimize the clock-feedthrough problem and introduce a technique for ultra low power operation by inducing dynamic voltage scaling. The current memory circuit was designed with BSIM3 model of $0.35{\mu}m$ process and was operated in the near-threshold region. From the simulation result, the clock-feedthrough could be minimized when designing the memory MOS Width of $2{\mu}m$, the switch MOS Width of $0.3{\mu}m$ and dummy MOS Width of $13{\mu}m$ in 1MHz switching operation. The power consumption was calculated with $3.7{\mu}W$ at the supply voltage of 1.2 V, near-threshold voltage.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.627-633
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• 2015

We designed of a LDO regulator with a OVP and UVLO protection function for a PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. The proposed LDO regulator is designed for low voltage input power protection. Proposed LDO circuit generated fixed 2.5 V from a supply of 3.3V. It was designed with 3.3 V power supply using a $0.35{\mu}m$ CMOS technology. SPICE simulation results showed that the proposed circuit provides 0.713 mV/V line regulation with output 2.5 V ~ 3.9 V and $8.35{\mu}V/mA$ load regulation with load current 0 mA to 40 mA.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.277-284
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• 2012

In this paper, we analyzed various noise in the video stream system that have largely influence on EMI noise. We presented the remedy for these various noises and then designed the wireless video streaming system for a vehicle. To minimize EMI noise, we derived the improvement of noise characteristic from impedance matching, new design of the inner layer of the PCB line design and new design of high-speed data Interfaces. As a result, the final system showed 40[dBuV/m] and 47[dBuV/m] dB in the each regulation band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.106-114
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• 2010

We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evolution to overcome a verification gap. The proposed platform includes a high level synthesis, and we develop a power-aware verification platform for low power design and verification automation using it's results. We developed a verification automation and power-aware verification methodology based on control and data flow graph (CDFG) and an abstract level language and RTL. The verification platform includes self-checking and the coverage driven verification methodology. Especially, the number of the random vector decreases minimum 5.75 times with the constrained random vector algorithm which is developed for the power-aware verification. This platform can verify a low power design with a general logic simulator using a power and power cell modeling method. This unified design and verification platform allow automatically to verify, design and synthesis the giga-scale design from the system level to RTL level in the whole design flow.

• Proceedings of the KIPE Conference
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• 2004.11a
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• pp.41-44
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• 2004

일반적으로 버크/부스트용 양방향 컨버터의 구현은 단 전원을 사용하는 각각의 PWM IC, 전류제어 PW 방식을 사용하게 된다. 이 경우 한쪽 모드로 동작시 다른 모드 제어기의 에러 앰프는 포화되기 때문에 모드 절환 동작시 마다 일정 시간 스위칭 동작을 멈추게 하는 회로가 필요하게 되어 원활한 방향 절환을 이룰 수 없게 된다. 본 연구에서는 양전원을 사용하는 하나의 제어기를 설계하여 방향 절환시의 문제점을 해결하고자 한다.

• The Journal of Korean Institute of Information Technology
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• v.16 no.12
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• pp.101-107
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• 2018

In wireless sensor network technology, which has been applied to various fields, the power supply and the power management of sensors are the most important issues. For this reason, a new concept of power supply and power management device is required. In this paper, we developed an autonomous independent power supply system that supplies the stable power to a sensor node without an additional external input by applying the energy harvesting technology using the electromagnetic induction principle by utilizing the current flowing in the transmission line. The proposed autonomous independent power supply system consists of a power supply using Power CT and a power management system including a charging circuit. The power management device uses a voltage limiter circuit and a monitoring circuit of charging voltage and current to ensure the safety of charging of the battery. In order to verify the performance of the proposed system, we applied it to the SVL diagnostic system and confirmed that it operates stably.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.245-246
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• 2012

ITER 초전도자석 전원공급장치의 예비설계가 실제 크기 6펄스 R&D 컨버터의 제작 및 시험결과를 기반으로 수행되었다. ITER 컨버터는 자체적으로 지지되는 알루미늄 버스바 구조로 제작되며, 이 버스바에 양면 클램핑 방식으로 조립되는 Thyristor 스위치는 4인치 규격으로써 컨버터의 종류에 따라 한 개의 암 당 8 - 16 개의 소자가 병렬로 구성된다. ITER 컨버터 예비설계는 알루미늄 버스바 구조설계, 컨버터 냉각설계, 컨버터 전기회로 설계, 컨버터 고장해석 및 보호설계, 시험절차 및 요건 등을 포함하며, 본 논문에서 그 설계결과를 기술한다. ITER 컨버터는 예비설계 결과를 기반으로 상세설계 및 제작설계를 거친 후 제작된다.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1043-1045
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• 2002

고전압 전원공급기를 고 밀도로 제작하기 위하여 고 주파수 동작을 시켜야 한다. 이에 따라 전원 공급기에서 최대의 부피를 차지하는 부품인 변압기는 원하는 주파수에서 최소의 부피로 충분한 전력을 수용하면서 완벽한 펄스재현을 하여야 한다. 고전압 전원공급기는 풀-브릿지 DC/DC 컨버트로 구성되어 있으며 스윗칭 주파수는 100 kHz 이다. 변압기는 일차권선이 1개이며 이차 권선은 4개로 구성된다 일차전압은 250 Vdc, 이차 권선 각각의 출력은 520 Vrms이다. 변압의 이차 권선은 배 전압 회로를 이용하여 승압 후 각각을 직렬로 연결하여 -4,100 VDC와 -2,050 VDC를 만들어 TWT(Travel Wave Tube)의 케소드 및 콜렉트에 공급한다. 이 변압기는 100 kHz 펄스로 동작하고 최대부피가 400$cm^3$이하가 되어야 한다. 본 논문에서는 이러한 변압기의 설계 방법 및 최소 온도상승을 위한 적절한 동작 자속밀도의 선택에 대하여 기술하고 변압기의 누설 인덕턴스, 분포 케페시턴스, 공진 주파수에 대하여 설계치 및 실험치를 비교 평가하였다.