• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.10-23
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• 2001

It is difficult to satisfy the QoS(Quality of Service) guarantee which is required by real-time application services only with the Best-Effort(BE) service adopted in the current Internet. Therefore, worldwide research is being made on the method of QoS provisioning. Among them, the QoS guarantee mechanism using the Diffserv(Differentiated Service) was discussed in this paper. First we analyzed how the DiffServ performance was affected by traffic models. For this, we performed the research for the random, bursts, and self-similar traffic modeling method. We then designed and implemented an OPNET simulator, and performed the simulation 7d performance evaluation for diverse input parameters. Based on the results of performance evaluation, it was confirmed that QoS guarantee is possible for the EF(Expedited Forwarding) class with the DiffServ function under every environments considered and the service separation between EF and BE(Best Effort) classes is also possible. We also analyzed the performance variation and dynamic behavior of DiffServ mechanism based on the resource allocation between E? and BE classes in WFQ(Weighted Fair Queueing).

• Journal of the Korea Society of Computer and Information
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• v.19 no.6
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• pp.81-92
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• 2014

In this paper, we propose an efficient dynamic workload balancing strategy which improves the performance of high-performance computing system. The key idea of this dynamic workload balancing strategy is to minimize execution time of each job and to maximize the system throughput by effectively using system resource such as CPU, memory. Also, this strategy dynamically allocates job by considering demanded memory size of executing job and workload status of each node. If an overload node occurs due to allocated job, the proposed scheme migrates job, executing in overload nodes, to another free nodes and reduces the waiting time and execution time of job by balancing workload of each node. Through simulation, we show that the proposed dynamic workload balancing strategy based on CPU, memory improves the performance of high-performance computing system compared to previous strategies.

• The KIPS Transactions:PartC
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• v.10C no.6
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• pp.727-738
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• 2003

Much research efforts are being exerted for the study of intrusion detection system(IDS). However little work has been for the communication medels and performance eveluation of the IDS. Here we present a communication framework for doing hybrid intrusion detection in which agents are used for local intrusion detections with a centralized data anaysis componenta for a global intrusion detection at multiple domains environment. We also assume the combination of host-based and network-based intrusion detection systems in the oberall framework. From the local domain, a set of information such as alert, and / or log data are reported to the upper level. At the root of the hierarchy, there is a global manager where data coalescing is performed. The global manager delivers a security policy to its lower levels as the result of aggregation and correlation of intrusion detection alerts. In this paper, we model the communication mechanisms for the hybrid IDS and develop a simular using OPNET modeller for the performance evaluation of transmission capabillities for the delivery of data and policy. We present and compare simulation results based on several scenarios focuding on communication delay.

• Proceedings of the Korea Society for Simulation Conference
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• 1992.10a
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• pp.2-2
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• 1992

최근 여러 분야에서 컴퓨터의 용도가 확산되고 더 높은 computing power에 대한 요구가 증가함에 따라, 컴퓨터의 성능을 향상시키기 위하여 프로세서의 고속화와 함께 시스템 구조의 개선을 위한 많은 연구가 진행되고 있다. 한 시스템내에 여러 개의 CPU들이 존재하는 다중프로세서 시스템(multiprocessor system) 구조를 가진 슈퍼미니급 중형 컴퓨터들은 상호연결망으로서 버스(bus) 방식을 많이 채택하고 있다. 버스 구조는 하드웨어가 간단하여 구현이 용이하지만, 여러 개의 시스템 지원들(프로세서들, 기억장치 모듈들 및 입출력 모듈들)이 버스를 공유하기 때문에 경합으로 인한 지연 시간이 발생하게 된다. 이러한 지연 시간으로 인한 성능 저하를 개선하는 방법으로는 버스 수의 증가와 최적 통제 프로토콜의 설계가 있다. 본 연구에서는 여러 개의 버스를 가진 다중프로세서 시스템에서 4가지 대표적인 버스 중재 프로토콜들에 대해 성능을 분석, 비교하여 최적 프로토콜을 제시하고자 한다. 이러한 대규모 하드웨어에 의하여 구현되는 시스템에서 주요 설계 요소들에 따른 시스템 성능 분석과 비교는 설계 단계에서 필수적인 과정이다. 그러나 하드웨어를 만들어서 분석하는 방법은 시간과 비용이 많이 소요되기 때문에 소프트웨어 시뮬레이션 방법이 널리 사용되고 있다. 본 연구팀에서는 시뮬레이션 전용언어인 SLAM II를 이용하여 다중프로세서 시스템의 시뮬레이터를 개발하고, 버스중재 프로토콜(bus arbitration protocol)을 용이하게 변경할 수 있도록 하여 각각의 성능을 비교하였다. 이 연구에서 비교된 프로토콜들은 고정-우선순위 방식(fixed-priority scheme), FIFO(first-in first-out) 방식, 라운드-로빈 방식(round-robin scheme), 및 회전-우선순위 방식(rotating-priority scheme) 등이다. 실험은 시스템의 주요 요소들인 프로세서와 기억장치 모듈 및 버스의 수들을 변경시킴으로써 다양한 시스템 환경에 대한 분석을 시도하였다. 작업 부하가 되는 기하장치 액세스 요구간 시간가격(inter-memory access request time interval)은 필요에 따라서 고정값 또는 확률 분포함수를 사용하였다. 특히, 실행될 프로그램의 특성에 따라 각 프로토콜의 성능이 다르게 나타날 수 있음을 검증하였으며, 기억장치의 지역성(memory locality)에 대한 프로토콜들의 성능도 비교하였다.

• Journal of Advanced Navigation Technology
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• v.27 no.1
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• pp.8-15
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• 2023

According to the results of a survey of pilots, 92% or 230 out of 252 respondents said they had experienced flight errors during flight. As so many pilots are experiencing Spatial Disorientation, and this is one of the main causes of aircraft accidents and loss of life, so it is important to understand accurately. However, in Korea, training equipment for fixed-wing pilots has already been developed and trained, or recently developed, and some equipment for helicopter pilots is available in the Korea Air Force, but there is no environment for helicopter pilots to receive training in Spatial Disorientation prevention. Therefore, we intend to produce a helicopter-only simulator, present a program to prevent possible Spatial Disorientation during flights for helicopter pilots, and propose legal and institutional measures based on future training data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.107-116
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• 2009

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.

• KIISE Transactions on Computing Practices
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• v.22 no.9
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• pp.426-440
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• 2016

Developed countries have already applied variable Intelligent Transportation System (ITS) technologies and have solved many transportation problems. Researchers also expect that ITS solutions can solve the transportation problems of Korean roads, when they are applied to Korean roads. However, since the existing ITS solutions applied in other countries are used for Korean roads without calibration, they will incur unexpected problems and high cost maintenance costs. In this paper, to solve the above problem, we propose the Korean Highway Traffic Analysis tool (KHTA). It not only analyzes all highway information in Korea, but also simulates the ITS algorithm implemented by traffic developers for the Korean highway environment. To test the stability, applicability and efficiency of the KHTA, we developed and analyzed the result of the ramp metering algorithm. The results show that the total travel time was reduced by 5 minutes compared to that without ramp metering, and traffic congestion was decreased. Thus, we confirmed that the KHTA can simulate ITS systems and can analyze the traffic environment in Korean highway. We expect that this tool would be very helpful to develop and analyze ITS systems in Korea.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8B
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• pp.668-676
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• 2012

In this paper, on the assumption that MPI collective communication function is converted into a group of point-to-point communication functions in the transaction level, an algorithm that optimizes broadcast, scatter and gather function among MPI collective communication is proposed. The MPI hardware engine that operates the proposed algorithm was designed, and it was named the OCC-MPE (Optimized Collective Communication Message Passing Engine). The OCC-MPE operates point-to-point communication by using the standard send mode. The transmission order is arranged according to the algorithm that proposes the most frequently used broadcast, scatter and gather functions among the collective communications, so the whole communication time is reduced. To measure the performance of the proposed algorithm, the OCC-MPE with the Bus Functional Model (BFM) based on SystemC was designed. After evaluating the performance through the BFM based on SystemC, the proposed OCC-MPE is designed by using VerilogHDL. As a result of synthesizing with the TSMC $0.18{\mu}m$, the gate count of each OCC-MPE is approximately 1978.95 with four processing nodes. That occupies approximately 4.15% in the whole system, which means it takes up a relatively small amount. Improved performance is expected with relatively small amounts of area increase if the OCC-MPE operated by the proposed algorithm is added to the MPSoC (Multi-Processor System on a Chip).