• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.9
• /
• pp.63-73
• /
• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.18 no.3
• /
• pp.42-51
• /
• 1981

Boron was predeposited into p (100) Si wafer at 94$0^{\circ}C$ for 60minutes to make the back surface field. High tempreature diffusion process at 1145$^{\circ}C$ for 3 hours was immediately followed without removing boron glass to obtain high surface concentration Back boron was annealed at 110$0^{\circ}C$ for 40minutes after boron glass was removed. N+ layer was formed by predepositing with POCI3 source at 90$0^{\circ}C$ for 7~15 minutes and annealed at 80$0^{\circ}C$ for 60min1es under dry Of ambient. The triple metal layers were made by evaporating Ti, Pd, Ag in that order onto front and back of diffused wafer to form the front grid and back electrode respectively. Silver was electroplated on front and back to increase the metal thickness form 1~2$\mu$m to 3~4$\mu$m and the metal electrodes are alloyed in N2 /H2 ambient at 55$0^{\circ}C$ and followed by silicon nitride antireflection film deposition process. Under artificial illumination of 100mW/$\textrm{cm}^2$ fabricated N+PP+ cells showed typically the open circuit voltage of 0.59V and short circuit current of 103 mA with fill factor of 0.80 from the whole cell area of 3.36$\textrm{cm}^2$. These numbers can be used to get the actual total area(active area) conversion efficiency of 14.4%(16.2%) which has been improved from the provious N+P cell with 11% total area efficiency by adding P+ back.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.9
• /
• pp.1847-1855
• /
• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.5
• /
• pp.87-97
• /
• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.33B no.11
• /
• pp.140-149
• /
• 1996

Cursive characters are written on an economical principle to reduce the motion of a pen in the limit of distinction between characters. That is, the pen is not lifted up to move for writing a next stroke, the pen is not moved at all, or connected two strokes chance their shapes to a similar and simple shape which is easy to be written. For these reasons, strokes and korean alphabets are not only easy to be changed, but also difficult to be splitted. In this paper, we propose a curvature stroke modeling method for splitting and matching by using a structural primitive. A curvature stroke is defined as a substroke which does not change its curvanture. Input strokes handwritten in a cursive style are splitted into a sequence of curvature strokes by segmenting the points which change the direction of rotation, which occur a sudden change of direction, and which occur an excessive rotation Each reference of korean alphabets is handwritten in a printed style and is saved as a sequence of curvature strikes which is generated by splitting process. And merging process is used to generate various sequences of curvature strikes for matching. Here, it is also considered that imaginary strokes can be written or omitted. By using a curvature stroke as a unit of recognition, redundant splitting points in input characters are effectively reduced and exact matching is possible by generating a reference curvature stroke, which consists of the parts of adjacent two korean alphasbets, even when the connecting points between korean alphabets are not splitted. The results showed 83.6% as recognition rate of the first candidate and 0.99sec./character (CPU clock:66MHz) as processing time.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.43 no.6 s.312
• /
• pp.28-35
• /
• 2006

Statistical models of shape variability based on active shape models (ASMs) have been successfully utilized to perform segmentation and recognition tasks in two-dimensional (2D) images. Three-dimensional (3D) model-based approaches are more promising than 2D approaches since they can bring in more realistic shape constraints for recognizing and delineating the object boundary. For 3D model-based approaches, however, building the 3D shape model from a training set of segmented instances of an object is a major challenge and currently it remains an open problem in building the 3D shape model, one essential step is to generate a point distribution model (PDM). Corresponding landmarks must be selected in all1 training shapes for generating PDM, and manual determination of landmark correspondences is very time-consuming, tedious, and error-prone. In this paper, we propose a novel automatic method for generating 3D statistical shape models. Given a set of training 3D shapes, we generate a 3D model by 1) building the mean shape fro]n the distance transform of the training shapes, 2) utilizing a tetrahedron method for automatically selecting landmarks on the mean shape, and 3) subsequently propagating these landmarks to each training shape via a distance labeling method. In this paper, we investigate the accuracy and compactness of the 3D model for the human liver built from 50 segmented individual CT data sets. The proposed method is very general without such assumptions and can be applied to other data sets.