• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.852-853
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• 2015

본 논문에서는 차량 추돌 방지 레이더용 24GHz 전압제어발진기를 제안한다. 제안한 회로는 TSMC $0.13-{\mu}m$ 고주파 CMOS 공정 ($f_T/f_{MAX}=120/140GHz$)으로 구현되어 있고, 1.5 볼트 전원전압에서 동작한다. 전체 칩 면적과 소비전력을 줄이기 위해 수동형 인덕터 대신 트랜지스터와 전류원으로 구성된 능동형 인덕터부를 사용하였다. 제작된 전압제어발진기는 기존 연구 결과에 비해 동작주파수에서 6.1mW의 낮은 소비전력 특성과 $0.06mm^2$의 매우 작은 칩 면적 특성을 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.630-633
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• 2001

본 논문에서는 2.3GHz대역의 WLL(무선가입자 회선망)에 사용하는 전압제어발진기를 설계하였다. 설계된 전압 제어 발진기는 3.2V, 10mA에서 동작하고 출력은 0.67dBm, 위상잡음 특성은 100kHz 옵셋 주파수에서 -102dBc/Hz이고 동조대역폭은 1V-3V의 전압변화에 2200∼2240MHz까지 40MHz의 동조 대역폭을 얻을 수 있었다. 따라서 제작된 전압제어 발진기는 무선가입자 회선망에 적용할 수 있다고 본다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.337-340
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• 2001

In this paper, we propose two types of dual-mode voltage controlled oscillators (VCO) for PCS/IMT-2000 applications. One is a VCO with controllable resonant circuit. The other type is a VCO with single output and two independent parts

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.2
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• pp.321-325
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• 2001

In this paper, we propose two types of dual-mode voltage cont.oiled oscillators (VCO) for PCS/IMT-2000 applications. One is a VCO with controllable resonant circuit. The other type is a VCO with single output and two independent parts.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.439-440
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• 2018

본 논문에서는 차량용 레이더를 위한 저 위상잡음 24GHz CMOS 전압제어발진기를 제안한다. 이러한 회로는 1.8볼트 전원에서 동작하며, 낮은 위상잡음을 가지도록 설계되어 있다. 제안한 회로는 TSMC $0.13{\mu}m$ 고주파 CMOS 공정으로 구현되어 있다. 제안한 회로는 최근 발표된 연구결과에 비해 저 전력동작에서 저 위상잡음 및 낮은 잡음지수 특성을 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.467-468
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• 2019

본 논문은 차량용 장거리 레이더를 위한 저 위상잡음 77GHz CMOS 전압제어발진기를 제안한다. 이러한 회로는 낮은 위상잡음을 가지도록 설계되어 있고, 1.5볼트 전원에서 동작한다. 제안한 회로는 TSMC $0.13{\mu}m$ 고주파 CMOS 공정으로 설계하였다. 제안한 회로는 최근 발표된 연구결과에 비해 저 위상잡음, 저 전력 및 적은 면적 특성을 보였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2205-2209
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• 2007

In this paper, a voltage controlled oscillator(VCO) of core components for wireless subscriber network is designed. The type of oscillator is colpits method and the oscillator device uses a LC resonator. The product is made on FR-4 substrate with dielectric constant of 4.6. The designed VCO is operated at 3.2V, 10mA and has output value of 0.67dB. The VCO's phase noise property is -102DBc/Hz at offset frequence of 100kHz. The fabricated VCO is the same as target value and can be used for wireless subscriber network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.87-93
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• 2010

This paper presents a low-power, wide tuning range VCO with automatic two-step negative-Gm calibration loop to compensate for the process, voltage and temperature variation. To cover the wide tuning range, digital automatic negative-Gm tuning loop and analog automatic amplitude calibration loop are used. Adaptive body biasing (ABB) technique is also adopted to minimize the power consumption by lowering the threshold voltage of transistors in the negative-Gm core. The power consumption is 2 mA to 6mA from a 1.2 V supply. The VCO tuning range is 2.65 GHz, from 2.35 GHz to 5 GHz. And the phase noise is -117 dBc/Hz at the 1 MHz offset when the center frequency is 3.2 GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.343-345
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• 2013

This paper describes a phase-locked loop (PLL) that generates a 51-phase clock with the operating frequency of 125MHz. To generate 51-phase clock with a frequency of 125 MHz, the proposed PLL uses three voltage controlled oscillators (VCOs) which are connected by resistors. Each VCO consists of 17 delay-cells. An resistor averaging scheme, which makes three VCOs to connect with each other, makes it possible to generates 51-phase clock of the same phase difference. The proposed PLL is designed by using 65 nm CMOS process with a 1.0 V supply. At the operating frequency of 125 MHz, the simulated DNL and peak-to-peak jitter are +0.0016/-0.0020 LSB and 1.07 ps, respectively. The area and power consumption of the implemented PLL are $290{\times}260{\mu}m^2$ and 2.5 mW, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.6
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• pp.231-237
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• 2016

This paper presents a multiband low phase noise CMOS VCO with wide frequency tunability using switched bondwire inductor bank. The combination of bondwire inductor and CMOS switch transistor enhances frequency tunability and improves phase noise characteristics. The proposed multiband VCO operates from 2.3GHz to 6.3GHz with phase noise of -136dBc/Hz and -122dBc/Hz at 1 MHz offset frequency, respectively. Switched bondwire inductor bank shows high quality factor(Q) at each frequency band, which allows better tradeoff between phase noise and power consumption. The proposed VCO is designed in TSMC 0.18um CMOS process and consumes 7.2 mW power resulting in figure of merit(FOM) of -189.3dBc/Hz at 1 MHz offset from 6GHz carrier frequency.