• Title/Summary/Keyword: 전압변조

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Ti:LiNbO3 three-waveguide type traveling-wave optical modulator; outer fed, anti-symmetrical Detuning (Ti:LiNbO3 세 도파로형 진행파 광변조기;바깥입사, 반대칭 Detuning)

  • 이우진;정은주;피중호;김창민
    • Korean Journal of Optics and Photonics
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    • v.15 no.4
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    • pp.375-384
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    • 2004
  • Switching phenomenon of a three-waveguide optical coupler was analyzed by using the coupled mode theory, and the coupling-length of the device was calculated by means of the FDM. CPW traveling-wave electrodes were designed by the CMM and SOR simulation techniques so as to satisfy the conditions of phase-velocity and impedance matching. Traveling-wave modulators were fabricated on a z-cut LiNbO$_3$ substrate. Ti was in-diffused in LiNbO$_3$ to make waveguides and Au electrodes were built on the waveguides by the electroplating technique. Insertion loss and switching voltage of the optical modulator were about 4 ㏈ and 15.6V. Network analyzer was used to obtain S parameters and corresponding RF response. From the measurement, parameters of the traveling-wave electrodes were extracted as such Z$_{c}$=39.2 $\Omega$, Neff=2.48, and a0=0.0665/cm((GHz) (1/2)). The measured optical response R(w) was compared with the theoretically estimated and both responses were shown to agree well. The measurement results revealed that the ㏈ bandwidth turned out to be about 13 GHz.

A Design of Wideband Frequency Synthesizer for Mobile-DTV Applications (Mobile-DTV 응용을 위한 광대역 주파수 합성기의 설계)

  • Moon, Je-Cheol;Moon, Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.5
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    • pp.40-49
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    • 2008
  • A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

A Wireless Video Streaming System for TV White Space Applications (TV 유휴대역 응용을 위한 무선 영상전송 시스템)

  • Park, Hyeongyeol;Ko, Inchang;Park, Hyungchul;Shin, Hyunchol
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.4
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    • pp.381-388
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    • 2015
  • In this paper, a wireless video streaming system is designed and implemented for TV white space applications. It consists of a RF transceiver module, a digital modem, a camera, and a LCD screen. A VGA resolution video is captured by a camera, modulated by modem, and transmitted by RF transceiver module, and finally displayed at a destination 2.6-inch LCD screen. The RF transceiver is based on direct-conversion architecture. Image leakage is improved by low pass filtering LO, which successfully covers the TVWS. Also, DC offset problem is solved by current steering techniques which control common mode level at DAC output node. The output power of the transmitter and the minimum sensitivity of the receiver is +10 dBm and -82 dBm, respectively. The channel bandwidth is tunable among 6, 7 and 8 MHz according to regulations and standards. Digital modem is realized in Kintex-7 FPGA. Data rate is 9 Mbps based on QPSK and 512ch OFDM. A VGA video is successfully streamed through the air by using the developed TV white-space RF communication module.

HF-Band Magnetic-Field Communication System Using Bias Switching Circuit of Class E Amplifier (E급 증폭기의 바이어스 스위칭 회로를 이용한 HF-대역 자기장 통신 시스템)

  • Son, Yong-Ho;Lee, June;Cho, Sang-Ho;Jang, Byung-Jun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.9
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    • pp.1087-1093
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    • 2012
  • In this paper, we implemented a HF-band magnetic-field communication system consisting of an amplitude shift keying(ASK) transmitter, a pair of loop antennas, and an ASK receiver. Especially, we suggested a new ASK transmitter architecture, where a drain bias of class E amplifier is switched alternatively between two voltage levels with respect to input data. A maximum 5 W class E amplifier was designed using a low cost IRF510 power MOSFET at the frequency of 6.78 MHz. A measured sensitivity of the designed ASK receiver is -78 dBm, which consists of a log amplifier, a filter, and a comparator. Maximum communication range of magnetic-wave communication system with loop antennas was calculated using magnetic field equations in both near-field and far-field ranges. Also, in order to verify the calculated values, an indoor propagation loss was measured using a pair of loop antennas whose dimensions are $30{\times}30cm$. Maximum operating range is estimated about 35 m in case of transmitter's output power of 1 W and receiver sensitivity of -70 dBm, respectively. Finally, the communication field test using the designed ASK transmitter and receiver was successfully done at the distance of 5 m.

A Design of PLL and Spread Spectrum Clock Generator for 2.7Gbps/1.62Gbps DisplayPort Transmitter (2.7Gbps/1.62Gbps DisplayPort 송신기용 PLL 및 확산대역 클록 발생기의 설계)

  • Kim, Young-Shin;Kim, Seong-Geun;Pu, Young-Gun;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.21-31
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    • 2010
  • This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.