• Title/Summary/Keyword: 전력 소모 분석

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A Design Procedure of Digitally Controlled Oscillator for Power Optimization (디지털 제어 발진기의 전력소모 최적화 설계기법)

  • Lee, Doo-Chan;Kim, Kyu-Young;Kim, Soo-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.5
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    • pp.94-99
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    • 2010
  • This paper presents a design procedure of digitally controlled oscillator(DCO) for power optimization. By controlling coarse tuning bits and fine tuning bits of DCO, the proposed design procedure can optimize the power dissipation and does not affect the LSB resolution, frequency range, linearity, portability. For optimization, the relationship between control bits and power dissipation of the DCO was analyzed. The DCO circuits using and unusing proposed design technique have been designed, simulated and proved using 0.13um, 1.2V CMOS library. The DCO circuit with proposed design technique has operation range between 283MHz and 1.1GHz and has 1.7ps LSB resolution and consumes 2.789mW at frequency of 1GHz.

Energy Efficient Sleep Scheduling By utilizing Response Time Slowdown of Concurrent HTTP Connection (다중 HTTP 연결의 응답시간 지연을 활용한 에너지 효율적 전력절약모드 스케줄링)

  • Jung, Choung-Il;Lim, In-Taek;Park, Chang-Yun
    • Proceedings of the Korean Information Science Society Conference
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    • 2007.06d
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    • pp.238-242
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    • 2007
  • 무선이동기기의 에너지 소모를 줄이기 위해서는 무선인터페이스의 전력소모를 최대한 줄이는 것이 중요하다. 대표적인 무선통신인 IEEE 802.11 표준에서는 무선인터페이스를 수면모드로 전환하는 전력절약모드(PSM, Power Save Mode)를 정의하고 있다 그러나 수면모드로 동작하는 도중에는 데이터를 수신할 수 없으므로 전력절약과 전송지연 사이에서 조정(trade-off)을 하여야 한다. HTTP와 같이 요청-응답을 기본으로 하는 통신 응용에서는 요청 발생 후 응답이 도착할 때까지 걸리는 시간을 노드의 수면시간에 반영하면 데이터의 수신이 지연되는 문제를 완화하면서 전력절약을 할 수 있으며, 기존 연구들도 이에 착안하는 기법을 제안하고 있다. 그러나 기존 연구들은 HTTP통신이 다중적으로 발생하면 그 효과는 사라지게 된다. 본 연구에서는 기존에 제안된 기법이 갖는 문제점을 분석하고 이를 완화하기위해 응답시간 지연비율을 적용한 지연수면(Delayed Sleep) 스케줄링 기법을 제안하며 시뮬레이션을 통해 이를 검증하였다.

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Low-Energy Intra-Task Voltage Scheduling using Static Timing Analysis (정적 시간 분석을 이용한 저전력 태스크내 전압 스케줄링)

  • Sin, Dong-Gun;Kim, Ji-Hong;Lee, Seong-Su
    • Journal of KIISE:Computer Systems and Theory
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    • v.28 no.11
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    • pp.561-572
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    • 2001
  • Since energy consumption of CMOS circuits has a quadratic dependency on the supply voltage, lowering the supply voltage is the most effective way of reducing energy consumption. We propose an intra-task voltage scheduling algorithm for low-energy hard real-time applications. Based on a static timing analysis technique, the proposed algorithm controls the supply voltage within an individual task boundary. By fully exploiting all the slack times, as scheduled program by the proposed algorithm always complete its execution near the deadline, thus achieving a high energy reduction ratio. In order to validate the effectiveness of the proposed algorithm, we built a software tool that automatically converts a DVS-unaware program into an equivalent low-energy program. Experimental results show that the low-energy version of an MPEG-4 encoder/decoder (converted by the software tool) consumes less than 7~25% of the original program running on a fixed-voltage system with a power-down mode.

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Dynamic Power Management Framework for Mobile Multi-core System (모바일 멀티코어 시스템을 위한 동적 전력관리 프레임워크)

  • Ahn, Young-Ho;Chung, Ki-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.7
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    • pp.52-60
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    • 2010
  • In this paper, we propose a dynamic power management framework for multi-core systems. We reduced the power consumption of multi-core processors such as Intel Centrino Duo and ARM11 MPCore, which have been used at the consumer electronics and personal computer market. Each processor uses a different technique to save its power usage, but there is no embedded multi-core processor which has a precise power control mechanism such as dynamic voltage scaling technique. The proposed dynamic power management framework is suitable for smart phones which have an operating system to provide multi-processing capability. Basically, our framework follows an intuitive idea that reducing the power consumption of idle cores is the most effective way to save the overall power consumption of a multi-core processor. We could minimize the energy consumption used by idle cores with application-targeted policies that reflect the characteristics of active workloads. We defined some properties of an application to analyze the performance requirement in real time and automated the management process to verify the result quickly. We tested the proposed framework with popular processors such as Intel Centrino Duo and ARM11 MPCore, and were able to find that our framework dynamically reduced the power consumption of multi-core processors and satisfied the performance requirement of each program.

Power Consumption Analysis of Asynchronous CSL mode MAC in Wi-SUN (Wi-SUN에서 비동기 CSL 모드 MAC의 전력소모 분석)

  • Yoon, Mi-Hee;Kim, Dongwon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.22 no.1
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    • pp.59-63
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    • 2022
  • In recent years, research on smart factory wireless mobile communication technology that wirelessly remotely controls utilities is being actively conducted. The Wi-SUN(Wireless Smart Utility Network) Alliance proposed Wi-SUN protocol structure suitable for building a platform such as a smart factory as a new wireless communication standardization standard based on EEE802.15.4g/e. It analyzes the performance of the IEEE802.15.4e CSL(Coordinated Sampled Listening) Mode MAC(Media Access Control) in terms of power consumption and looks at considerations for efficient operation. Although CSL-MAC can dramatically reduce power consumption at the receiving end in an asynchronous manner, it has been found that the transmitting end has a disadvantage in that power consumption occurs due to an excessive wake-up sequence.

MAC Layer Protocol for Improvement in Power Consumption and Time Delay in a Sensor Network (센서 네트워크에서 전력소모와 지연시간 개선을 위한 MAC 계층 프로토콜 연구)

  • Shin, Jae Kwan;Park, Dong Chan;Kim, Suk Chan
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.2
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    • pp.366-368
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    • 2015
  • This paper proposes a MAC protocol for sensor networks such as disaster detection system which generate the non-periodic packet. B-MAC has been used to solve delay problem for sensor networks, however, the power loss occurs due to excessive preamble and over-hearing. In contrast, S-MAC has a number of drawbacks in power consumption due to synchronization. In this paper, we propose H-MAC and analyze its performance which has improved power consumption compared to S-MAC and overhead and over-hearing compared to B-MAC.

A network condition adaptive reliable transport protocol for wireless sensor networks (무선 센서 네트워크를 위한 네트워크 환경에 적응하는 신뢰성 있는 전송규약)

  • Yim, Keun-Soo;Park, Jeong-Tea;Koh, kern
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.04d
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    • pp.277-279
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    • 2003
  • 본 논문에서는 편재 컴퓨팅(ubiquitous and pervasive computing) 환경에 입력 시스템으로 사용하는 센서 네트워크에서 측정한 데이터의 품질 (sampling rate and quantization depth) 을 보증하며 네트워크 트래픽 또는 소모전력과 같은 비용을 최소화하기 위한 방법으로, 휴리스틱 알고리즘에 의한 비주기적 샘플링과 신뢰성 있는 전송규약을 사용하는 비주기적 전송방식을 제안한다. 그리고 제안한 비주기적 전송방식에 핵심기술인 신뢰성 있는 전송 규약의 비용을 최적화하기 위한 방법으로 ACK방식과 NACK방식을 패킷 에러율과 동일한 라우터를 사용하는 이웃 노드의 수와 같은 네트워크 상황에 따라 상보적으로 사용하는 상보적 방식(alternative method)을 제안하고, 전체 통신규약을 설계하며, 해석을 통해 성능을 분석하고, 네트워크 상태에 따라 두 방식의 성능상의 우열이 전환되는 전환점을 유도한다. 제안하는 상보형 신뢰성 있는 전송규약은 전체 센서 네트워크에서 처리되는 패킷의 비트 수를 최소화해, 각 노드의 총 전력 소모의 20-60%를 차지하는 통신모듈의 소비 전력을 줄일 수 있어 전력소모를 크게 개선 할 수 있다. 나아가서 다양한 센서 네트워크에서 설계한 전송규약을 바탕으로 하는 제안하는 비주기적 전송방식을 활용한다면 최적의 비용으로 측정하는 데이터의 품질을 보증할 수 있다.

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Robust Signal Transition Density Estimation by Considering Reconvergent Path (재수렴성 경로를 고려한 견실한 신호 전이 밀도 예측)

  • Kim, Dong-Ho;U, Jong-Jeong
    • The KIPS Transactions:PartA
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    • v.9A no.1
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    • pp.75-82
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    • 2002
  • A robust signal transition density propagation method for a zero delay model is presented to obtain the signal transition density for estimating the power consumption. The power estimation for the zero delay model is a proper criteria for the lower boundary of power consumption. Since the input characteristics are generally unknown at design stage, robust estimation for wide range input characteristics is very important for the power consumption. In this paper, a conventional transition estimation method will be explored. And this exploration will be analyzed with the input/output signal transition behavior and used to propose the robust signal transition density propagation for the power estimation. In order to apply to practical circuits, the reconvergent path, which is crucial to affect the exactness of the power estimation, will be studied and an algorithm to take the reconvergent path into consideration will be presented. In experiment, the proposed methodology shows better robustness, comparable accuracy and elapsed time compared to the conventional methods.