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Three-dimensional Model Generation for Active Shape Model Algorithm (능동모양모델 알고리듬을 위한 삼차원 모델생성 기법)

  • Lim, Seong-Jae;Jeong, Yong-Yeon;Ho, Yo-Sung
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.43 no.6 s.312
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    • pp.28-35
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    • 2006
  • Statistical models of shape variability based on active shape models (ASMs) have been successfully utilized to perform segmentation and recognition tasks in two-dimensional (2D) images. Three-dimensional (3D) model-based approaches are more promising than 2D approaches since they can bring in more realistic shape constraints for recognizing and delineating the object boundary. For 3D model-based approaches, however, building the 3D shape model from a training set of segmented instances of an object is a major challenge and currently it remains an open problem in building the 3D shape model, one essential step is to generate a point distribution model (PDM). Corresponding landmarks must be selected in all1 training shapes for generating PDM, and manual determination of landmark correspondences is very time-consuming, tedious, and error-prone. In this paper, we propose a novel automatic method for generating 3D statistical shape models. Given a set of training 3D shapes, we generate a 3D model by 1) building the mean shape fro]n the distance transform of the training shapes, 2) utilizing a tetrahedron method for automatically selecting landmarks on the mean shape, and 3) subsequently propagating these landmarks to each training shape via a distance labeling method. In this paper, we investigate the accuracy and compactness of the 3D model for the human liver built from 50 segmented individual CT data sets. The proposed method is very general without such assumptions and can be applied to other data sets.

Effects of Supplemental Lighting on Growth and Yield of Sweet Pepper (Capsicum annuum L.) in Hydroponic Culture under Low Levels of Natural Light in Winter (동계시설내 보광이 수경재배 착색단고추(Capsicum annum L.)의 생육에 미치는 영향)

  • Kim, Yong-Bum;Bae, Jong-Hyang;Park, Me-Hea
    • Horticultural Science & Technology
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    • v.29 no.4
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    • pp.317-325
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    • 2011
  • This study was conducted to examine the effect of supplemental lighting on the growth and yield of hydroponically grown sweet pepper (Capsicum annuum L. cv. sprit) under low levels of natural light in winter. The plants were treated with natural light only (control), 3-hour supplemental lighting before sunrise, after sunrise and after sunset with high pressure sodium (HPS, 400W). As the result of these three treatments, the supplemental lighting promoted photosynthesis in the low light intensity condition and particularly photosynthesis was more active right after sun rise in the morning, 1.5-$3.0{\mu}molCO_2{\cdot}m^{-2}{\cdot}s^{-1}$ comparing to those of supplemental lighting after sunset, 0.5-$1.5{\mu}molCO_2{\cdot}m^{-2}{\cdot}s^{-1}$. Transpiration rate and stomatal conductance sharply increased with supplemental lighting after sunrise then they decreased again after turning the lights off. Stomatal size was observed $32.2{\mu}m^2$ after supplemental lighting, whereas the size of the natural light was almost closed at $7.7{\mu}m^2$. The average plant height of sweet papper cv. spirit was 185 cm before sunrise, 188 cm after sunrise and 208 cm after sunset with supplemental lighting for 3hours while the control was 171 cm. With supplemental lighting a better number of fruit set per plant was measured 4.3 before and after sunrise, 3.7 after sunset but 2.6 in the control. Interestingly, there were no significant differences in the sugar content ($^{\circ}Brix$) degree between treatment of supplemental lighting, whereas slight differences between seasons were seen. The marketable fruit yield of sweet pepper (cv. spirit) was $116.0kg{\cdot}ha$ with supplemental lighting, whereas the control (natural light only) was $75.8kg{\cdot}ha$. Despite of spending electricity and depreciation cost, the economic analysis showed net income with supplemental lighting after sunrise was 51% higher than control treatment in cv. spirit.

Nonthermal Plasma-assisted Diesel Reforming and Injection of the Reformed Gas into a Diesel Engine for Clean Combustion (디젤의 청정연소를 위한 저온 플라즈마 연료개질 및 개질가스의 디젤엔진 첨가에 관한 연구)

  • Kim, Seong-Soo;Chung, Soo-Hyun;Kim, Jin-Gul
    • Journal of Korean Society of Environmental Engineers
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    • v.27 no.4
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    • pp.394-401
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    • 2005
  • A nonthermal plasma-assisted fuel reformer was developed and the effects of operating variables on the performance of this reformer were studied. The $H_2$-rich reformed gas from the reformer was injected into a diesel engine under an idle condition and the effects of the amount of injected gas on the NO and soot reduction were investigated. It was found that with increasing electric power consumption, the degree of facility of ignition of the reforming reaction in the reformer could be enhanced. The performance of the reformer including $H_2$ concentration, $H_2$ recovery, and energy conversion was affected only by the O/C mole ratio. This was because the equilibrium reaction temperature was governed by the O/C mole ratio. With increasing O/C mole ratio, the $H_2$ recovery and energy conversion passed through the maximum values of 33.4% and 66%, respectively, at an O/C mole ratio between 1.2 and 1.5. The reason why the $H_2$ recovery and energy conversion increased with increasing O/C mole ratio when the O/C mole ratio was lower than $1.2{\sim}1.5$ appeared to be that the complete oxidation reaction occurred more enough with increasing O/C mole ratio in this low O/C mole ratio range and accordingly the reaction temperature increased. Whereas the reason why the $H_2$ recovery and energy conversion decreased with increasing O/C mole ratio when the O/C mole ratio was higher than $1.2{\sim}1.5$ appeared to be that the complete oxidation reaction was further advanced and the $H_2$ recovery and energy conversion decreased. As the weight ratio of reformed diesel to total diesel which entered the diesel engine was increased to $18.2{\sim}23.5%$, NO and soot reduction efficiencies increased and reached as values high as 68.5% and 23.5%, respectively.

Development of Embedded Board for Integrated Radiation Exposure Protection Fireman's Life-saving Alarm (일체형 방사선 피폭 방호 소방관 인명구조 경보기의 임베디드 보드 개발)

  • Lee, Young-Ji;Lee, Joo-Hyun;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.23 no.4
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    • pp.1461-1464
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    • 2019
  • In this paper, we propose the development of embedded board for integrated radiation exposure protection fireman's life-saving alarm capable of location tracking and radiation measurement. The proposed techniques consist of signal processing unit, communication unit, power unit, main control unit. Signal processing units apply shielding design, noise reduction technology and electromagnetic wave subtraction technology. The communication unit is designed to communicate using the wifi method. In the main control unit, power consumption is reduced to a minimum, and a high performance system is formed through small, high density and low heat generation. The proposed techniques are equipment operated by exposure to poor conditions, such as disaster and fire sites, so they are designed and manufactured for external appearance considering waterproof and thermal endurance. The proposed techniques were tested by an authorized testing agency to determine the effectiveness of embedded board. The waterproof grade has achieved the IP67 rating, which can maintain stable performance even when flooded with water at the disaster site due to the nature of the fireman's equipment. The operating temperature was measured in the range of -10℃ to 50℃ to cope with a wide range of environmental changes at the disaster site. The battery life was measured to be available 144 hours after a single charge to cope with emergency disasters such as a collapse accident. The maximum communication distance, including the PCB, was measured to operate at 54.2 meters, a range wider than the existing 50 meters, at a straight line with the command-and-control vehicle in the event of a disaster. Therefore, the effectiveness of embedded board for embedded board for integrated radiation exposure protection fireman's life-saving alarm has been demonstrated.

An Area-Efficient Time-Shared 10b DAC for AMOLED Column Driver IC Applications (AMOLED 컬럼 구동회로 응용을 위한 시분할 기법 기반의 면적 효율적인 10b DAC)

  • Kim, Won-Kang;An, Tai-Ji;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.5
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    • pp.87-97
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    • 2016
  • This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

Influence of Glass Dielectric Property on the External Electrode Fluorescent Lamps (유리관의 유전 특성이 외부전극 형광램프에 미치는 영향)

  • Shin, Myeong-Ju;Jeong, Jong-Mun;Kim, Jung-Hyun;Kim, Ga-Eul;Lee, Mi-Ran;Yoo, Dong-Gun;Koo, Je-Huan;Hong, Byoung-Hee;Choi, Eun-Ha;Cho, Guang-Sup
    • Journal of the Korean Vacuum Society
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    • v.16 no.5
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    • pp.330-337
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    • 2007
  • Influence of glass dielectric property (dielectric constant K, dielectric loss) on the external electrode fluorescent lamps of the dielectric barrier discharge has been investigated with 4-different glasses. Conventional borosilicate glass tubes with $K=5.6{\sim}5.9$ and tan ${\delta}=5.0{\times}10^{-3}{\sim}6.0{\times}10^{-3}$ and aluminosilicate glass tubes with high K=6.6 and low tan ${\delta}=1{\times}10^{-4}$ and soda-lime glass tribes with K=7.7 and tan ${\delta}=1.37{\times}10^{-2}$ have been compared. The high value of dielectric constant K makes the capacitance of external electrode fluorescent lamps intensity and enhances the discharge efficiency. The dielectric loss of tan ${\delta}$ shows the factor of power consumption in the external electrode to induce heats and to be weak in pinhole stability. The aluminosilicate glass tubes of high K and low tan ${\delta}$ have been enhanced by $14{\sim}18%$ in luminance and efficiency in comparison with the conventional borosilicate glass tubes and the aluminosilicate external electrode fluorescent lamps are strong against the pinhole formation. Soda-lime glass tubes with high K and high tan ${\delta}$ are a little favorable in luminance and efficiency and they are very weak in pinhole occurrence.

A Design of PLL and Spread Spectrum Clock Generator for 2.7Gbps/1.62Gbps DisplayPort Transmitter (2.7Gbps/1.62Gbps DisplayPort 송신기용 PLL 및 확산대역 클록 발생기의 설계)

  • Kim, Young-Shin;Kim, Seong-Geun;Pu, Young-Gun;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.21-31
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    • 2010
  • This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

An Experiment and Analysis for Standardize Measurement on CCFL (냉음극 형광램프의 표준화 계측을 위한 실험과 분석)

  • Jin, Dong-Jun;Jeong, Jong-Mun;Jeong, Hee-Suk;Kim, Jin-Shon;Lee, Min-Kyu;Kim, Jung-Hyun;Koo, Je-Huan;Gwon, Gi-Cheong;Kang, June-Gill;Choi, Eun-Ha;Cho, Guang-Sup
    • Journal of the Korean Vacuum Society
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    • v.17 no.4
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    • pp.331-340
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    • 2008
  • A method of measuring the current and voltage is suggested in the circuit of cold cathode fluorescent lamps (CCFLs) which are driven at a high frequency of $50{\sim}100\;kHz$ and a high voltage of several kV. It is difficult to measure the current and voltage in the lamp circuit, because the impedance of the probe at high voltage side causes the leakage current and the variation of luminance. According to the analysis of equivalence circuit with the probe impedance and leakage current, the proper measuring method is to adjust the input DC voltage and to keep the specific luminance when the probe is installed at a high voltage circuit. The lamp current is detected with a current probe or a high frequency current meter at the ground side and the voltage is measured with a high voltage probe at the high voltage side of lamp. The lamp voltage($V_C$) is measured between the ballast capacitor and the lamp electrode, and the output voltage($V_I$) of inverter is measured between inverter output and ballast capacitor. As the phases of lamp voltage($V_C$) and current ($I_G$) are nearly the same values, the real power of lamp is the product of the lamp voltage($V_C$) by the lamp current($I_G$). The measured value of the phase difference between inverter output voltage($V_I$) and lamp current($I_G$) is appreciably deviated from the calculated value at $cos{\theta}=V_C/V_I$.

A Study on Establishment of the Optimum Mountain Meteorological Observation Network System for Forest Fire Prevention (산불 방지를 위한 산악기상관측시스템 구축방안)

  • Lee, Si-Young;Chung, Il-Ung;Kim, Sang-Kook
    • Korean Journal of Agricultural and Forest Meteorology
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    • v.8 no.1
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    • pp.36-44
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    • 2006
  • In this study, we constructed a forest fire danger map in the Yeongdong area of Gangwon-do and Northeastern area of Gyeongsangbuk-do using a forest fire rating model and geographical information system (GIS). We investigated the appropriate positions of the automatic weather station (AWS) and a comprehensive network solution (a system including measurement, communication and data processing) for the establishment of an optimum mountain meteorological observation network system (MMONS). Also, we suggested a possible plan for combining the MMONS with unmanned monitoring camera systems and wireless relay towers operated by local governments and the Korea Forest Service for prevention of forest fire.

A 13b 100MS/s 0.70㎟ 45nm CMOS ADC for IF-Domain Signal Processing Systems (IF 대역 신호처리 시스템 응용을 위한 13비트 100MS/s 0.70㎟ 45nm CMOS ADC)

  • Park, Jun-Sang;An, Tai-Ji;Ahn, Gil-Cho;Lee, Mun-Kyo;Go, Min-Ho;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.3
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    • pp.46-55
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    • 2016
  • This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.