• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• 한국신재생에너지학회:학술대회논문집
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• 2007.06a
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• pp.485-488
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• 2007

$SF_6$(sulfur hexafluoride)는 뛰어난 단열 및 아크방지능력(arc-extinguishingproperty)으로 인해, 전력용 변압기의 절연가스와 반도체${\cdot}$액정용 플라즈마 CVD로의 cleaning gas, 주물공장 covering gas 등으로 사용되고 있다. 하지만, $SF_6$의 지구온난화지수(global warming potential)는 $CO_2$대비 23,900배가 높아 기후변화에 미치는 영향이 $CO_2$보다 훨씬 크고, 대기 중 분해되지 않고 잔존하는 기간이 $CH_4$ 10년, $CO_2$ 및 CFCs는 100년으로 추정되는데 반해, $SF_6$는 3,200년으로 연간방출양이 작더라도 오랜 기간 누적되면 그 파장이 클 것으로 사료된다. 대부분의 가스 하이드레이트(고상결정상태)는 고압, 저온에서 형성가능 하지만, 불화가스에 대해서는 쉽게 결정화가 일어난다. $SF_6$는 3$^{\circ}C$, 2기압에서 고밀도 고상화가 되기 때문에 여러 기체와 흔합되어 있는 경우 $SF_6$만을 압축된 고상 결정상태를 형성, $SF_6$를 회수, 정제할 수 있으므로 불화가스 분리${\cdot}$회수에 기술적, 경제적 효과를 기대할 수 있다. 본 연구에서는 하이드레이트 촉진제로서 계면활성제(promoter) 첨가에 따른 $SF_6$ 하이드레이트 형성 및 해리과정 실험을 통해 효율적인 $SF_6$ 저감에 관한 적용기술을 연구해 보았다.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.1-4
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• 2001

We have fabricated and evaluated a new Si pin photodetector for APF optical link. The fabricated device has the $p^{+}$-guard ring around the metal-semiconductor contact and the web patterned $p^{+}$-shallow diffused region in the light absorbing area. From the measurements of electo-optical characteristics under the bias of -5 V, the junction capacitance of 4 pF and the dark current of 180 pA were obtained. The optical signal current of 1.22 $\mu$A and the responsivity of 0.55 A/W were obtained when the 2.2 $\mu$W optical power with peak wavelength of 670 nm was incident on the device. The fabricated device showed the maximum spectral response in a spectrum of 650-700 nm. It is expected that the fabricated device can be very useful for detecting the optical signal in the application of red light optics.

• Journal of IKEEE
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• v.12 no.1
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• pp.1-7
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• 2008

With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.81-85
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• 2013

Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.

• Fire Science and Engineering
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• v.20 no.1 s.61
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• pp.71-76
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• 2006

The major causes of electrical fire are classified to short circuit fault, overload fault, electric leakage and electric contact failure. The occurrence factor of the fire is electric arc or spark accompanied with electrical faults. Residual Current Protective Device(RCD) of high sensitivity type used at low voltage wiring cuts off earth leakage and overload, but the RCD can't cut off electric arc or spark to be a major factor of electrical fire. As the RCDs which are applied low voltage distribution panel are prescribed to rated breaking time about 30[ms](KS C 4613), the RCDs can't perceive to the periodic electric arc or spark of more short wavelength level. To be improved on such problem, this paper is proposed to a auxiliary control apparatus for RCD trip on electric arc or spark due to electrical fire. Some experimental results of the proposed apparatus is confirmed to the validity of the analytical results.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.31-35
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• 2006

This paper is studied on a protective control system for electrical fire used electrical characteristics of SCR and multilayer-type PTC thermistor. The PTC thermistor has characteristic or positive resistivity temperature coefficient according to the temperature variation, which is construction of a regular square and cube demarcation with $BaTiO_{3_}$Ceramics of positive temperature coefficient. Also PTC shows the phenomenon which is rapidly increased in the resistivity if the temperature is increased over Curie temperature point. This paper is proposed on a protective control system used multilayer-type PTC which is protected from electrical fire due to electric short circuit faults or overload faults. Some experimental results of the proposed apparatus is confirmed to the validity of the analytical results.

• Journal of the Korean Society for Railway
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• v.13 no.5
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• pp.504-508
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• 2010

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide under the environment that radiation exists. The energy loss will be also studied as the inductance values are changed. In this paper, the electrical characteristics are simulated by SPICE, and compared for variation of inductance and threshold voltage based on IGBT.

• Journal of Sensor Science and Technology
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• v.4 no.2
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• pp.7-13
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• 1995

A new FET type semiconductor pressure sensor (PSFET : pressure sensitive field effect transistor) was fabricated and its operational characteristics were investigated. A ZnO thin film as a piezoelectric layer, $5000{\AA}$ thick, was deposited on a gate oxide of FET by RF magnetron sputtering. The deposition conditions to obtain a c-axis poling structure were substrate temperature of $300^{\circ}C$, RF power of 140watt, and working pressure of 5mtorr in Ar ambience. The fabricated PSFET device showed good linearity and stability in the applied pressure range($1{\times}10^{5}\;Pa{\sim}4{\times}10^{5}\;Pa$).

• Journal of the Korean Vacuum Society
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• v.6 no.3
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• pp.267-274
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• 1997

Silicon shallow trenches applied to the STI (Shallow Trench Isolation) of integrated circuits were etched using inductively coupled $Cl_2$ and HBr/$Cl_2$ plasmas and the effects of process parameters on the etch profiles of silicon trenches and the physical damages on the trench sidewall and bottom were investigated. The increase of inductive power and bias voltage in $Cl_2$ and HBr/$Cl_2$ plasmas increased polysilicon etch rates in general, but reduced the etch selectivities over nitride. In case of $Cl_2$ plasma, low inductive power and high bias voltage showed an anisotropic trench etch profile, and also the addition of oxygen or nitrogen to chlorine increased the etch anisotropy. The use of pure HBr showed a positively angled etch profile and the addition of $Cl_2$ to HBr improved the etch profile more anisotropically. HRTEM study showed physical defects formed on the silicon trench surfaces etched in $Cl_2/N_2$ or HBr/ $Cl_2$ plasmas.