• The Journal of the Acoustical Society of Korea
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• v.22 no.3
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• pp.188-193
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• 2003

Regardless of the distribution of the adaptation data in the testing environment, model-based adaptation methods that have so far been reported in various literature incorporates the adaptation data undiscriminatingly in reducing the mismatch between the training and testing environments. When the amount of data is small and the parameter tying is extensive, adaptation based on outlier data can be detrimental to the performance of the recognizer. The distribution of the adaptation data plays a critical role on the adaptation performance. In order to maximally improve the recognition rate in the testing environment using only a small number of adaptation data, supervised weighted training is applied to the structural maximum a posterior (SMAP) algorithm. We evaluate the performance of the proposed weighted SMAP (WSMAP) and SMAP on TIDIGITS corpus. The proposed WSMAP has been found to perform better for a small amount of data. The general idea of incorporating the distribution of the adaptation data is applicable to other adaptation algorithms.

• Journal of KIISE:Software and Applications
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• v.36 no.6
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• pp.451-461
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• 2009

The Adaptive Random Testing(ART) aims to improve the performance of traditional Random Testing(RT) by reducing the number of test cases to find the failure region which is located in the input domain. Such enhancement can be obtained by efficient selection algorithms of test cases. The ART through Iterative Partitioning(IP-ART) is one of ART techniques and it uses an iterative input domain partitioning method to improve the performance of early-versions of ART which have significant drawbacks in computation time. And the IP-ART with Enlarged Input Domain(EIP-ART), an improved version of IP-ART, is known to make additional performance improvement with scalability by expanding to virtual test space beyond real input domain of IP-ART. The EIP-ART algorithm, however, have the drawback of heavy cost of computation time to generate test cases mainly due to the virtual input domain enlargement. For this reason, two algorithms are proposed in this paper to mitigate the computation overhead of the EIP-ART. In the experiments by simulations, the tiling technique of input domain, one of two proposed algorithms, showed significant improvements in terms of computation time and testing performance.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2021.06a
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• pp.49-51
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• 2021

Versatile Video Coding(VVC)에서 동영상 압축 효율을 증가시키기 위한 다양한 화면 간 예측(inter prediction) 기법 중에 적응적 움직임 벡터 해상도(Adaptive motion vector resolution, 이하 AMVR) 기술이 채택되었다. 다만 AMVR을 위해서는 다양한 움직임 벡터 해상도를 테스트해야 하는 부호화 복잡도를 야기하였다. AMVR의 부호화 복잡도를 줄이기 위하여, 본 논문에서는 가벼운 신경망 모델 기반의 AMVR 조기 판별 기법을 제안한다. 이에 따라 불필요한 상황을 미리 조기에 인지하여 대응한다면 나머지 AMVR 과정을 생략할 수 있기에 부호화 복잡도의 향상을 볼 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2C
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• pp.315-323
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• 2004

In this paper we present a method to generate the bit stream of static video test patterns for testing the picture quality in DTV system. The proposed user-defined quantization table is suitable for the static video test pattern and for minimizing the deterioration of picture quality by quantization, the underflow or overflow of video buffer generated on the process of coding the static video test pattern is compensated by a adaptive zero stuffing algorithm so that optimal picture quality is implemented. Experimental result showed that the test pattern stream encoded by MPEG-2 software with the proposed algorithm had a stable bit rate and good video quality during the decoding process, which is about 3 dB higher than that of the conventional case.

• Journal of Internet Computing and Services
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• v.12 no.3
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• pp.17-26
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• 2011

We have developed a wearable device that can convert sensor data into real-time step counts. Sensor data on gait were acquired using a triaxial accelerometer. A test was performed according to a test protocol for different walking speeds, e.g., slow walking, walking, fast walking, slow running, running, and fast running. Each test was carried out for 36 min on a treadmill with the participant wearing an Actical device, and the device developed in this study. The signal vector magnitude (SVM) was used to process the X, Y, and Z values output by the triaxial accelerometer into one representative value. In addition, for accurate step-count detection, we used three algorithms: an heuristic algorithm (HA), the adaptive threshold algorithm (ATA), and the adaptive locking period algorithm (ALPA). The recognition rate of our algorithm was 97.34% better than that of the Actical device(91.74%) by 5.6%.

• Journal of Broadcast Engineering
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• v.27 no.4
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• pp.511-518
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• 2022

Supervised learning based on deep learning has made a leap forward in various application fields. However, many supervised learning methods work under the common assumption that training and test data are extracted from the same distribution. If it deviates from this constraint, the deep learning network trained in the training domain is highly likely to deteriorate rapidly in the test domain due to the distribution difference between domains. Domain adaptation is a methodology of transfer learning that trains a deep learning network to make successful inferences in a label-poor test domain (i.e., target domain) based on learned knowledge of a labeled-rich training domain (i.e., source domain). In particular, the unsupervised domain adaptation technique deals with the domain adaptation problem by assuming that only image data without labels in the target domain can be accessed. In this paper, we explore the unsupervised domain adaptation techniques.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.208-210
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• 2003

본 논문은 SOC 내에 존재하는 코아들을 테스트하는 과정에서 개별 코아들의 테스트 조건을 기반으로 한 스케듈링을 통해 최적의 Test ing time을 구하는 연구이다. SOC 내에 존재하는 코아들은 주어지는 TAM(Test Access Mechanism) Width에 따라 각코아들의 Width가 달라지고, 최대 Width에서 최소 Width(1)까지 각 Width 별로 Testing time을 계산할 수 있다. 코아들의 각 Width 별 Testing time을 기존의 Rectangle Packing Algorithm을 수정, 보완하여 효율적으로 구성한 수정 Rectangle Packing Algorithm에 적응하여 최적의 Testing time을 구하는 것이 본 논문의 목적이다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.703-706
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• 2004

공정기술의 발달과 컴퓨터 구조적인 발전에 의해서, 시스템의 동작속도가 기하급수적으로 증가하고 있다. 동작속도의 증가는 CMOS로 구현된 chip의 RC 특성에 의해서 timing variation 문제가 발생할 가능성이 높아지면서 테스트 비용이 전체 설계비용에서 차지하게 되는 비중이 급격하게 증가하고 있다. 따라서 온라인 테스트와 진화하드웨어 등이 테스트 비용감소를 위해서 연구되고 있다. 본 논문에서는 네트워크프로세서의 생존성을 위해서, 패킷엔진의 pipline의 각 stage사이의 clock slack borrowing을 이용해서 timing variation 문제를 자체적으로 해결할 수 있다는 것을 mixed-mode simulation을 통해서 통합 검증하였다. 또한 기존의 off-chip 진화하드웨어에 비해서 on-chip구현을 통해서 진화하드웨어의 성능향상과 메모리에 의해서 발생하는 overhead를 감소시키는 것이 가능함을 확인했다.

• Journal of Families and Better Life
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• v.12 no.2
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• pp.118-128
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• 1994

본 연구의 목적은 알콜중독가정에서 성장한 성인자녀들의 적응도에 영향을 미치는 요인들간의 인과관계를 설명해줄 수 있는 이론적 인과관계모델을 개발하고 그 모델의 적합 성(fit of the model)에 대해 연구되었다 본 연구의 이론적 인과관계모델은 가족 체계이론 대응이론 사회지원이론, 그리고 사회학습이론에 기초를 두고 개발되었다. 본 연구자에 의해 개발된 이론적 인과관계모델은 표보의 특성을 좀 더 적절하게 설명할 수 있고 모델의 적합 성을 증진시키기 위해 수정된 인과관계모델을 바탕으로 연구되었다. 본 연구의 결과를 요약 하면 다음과 같다. 1) 사회적지원의 이용성을 인식하는 성인 자녀들의 경우 정서적으로 불 안정한 상태를 초래했으며 ;2) 사회적지원은 삶에 대한 적응도에 긍정적인 영향을 미쳤고; 3) 정서적으로 안정된 성인자녀들의 경우 글의 삶에 좀 더나은 적응도를 나타내는데 영향을 미쳤다 본 연구에서는 또한 사회적지원과 성인자녀들의 정서적 상태간의 부정적 인관관계에 대해 논의 되었으며 본 연구의 결과를 바탕으로 상담현장에서의 실제 활용에 대해서도 논의 되었다.

• Journal of IKEEE
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• v.17 no.2
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• pp.168-175
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• 2013

The delay times due to the propagating of data on PCB depend on the shape and length of interconnection lines when memory controllers and high speed memories are soldered on the PCB. The dependency on the placement and routing on the PCB requires redesign of I/O logic or reconfiguration of the memory controller after the delay time is measured if the controller is programmable. In this paper, we propose architecture of configuring logic for the delay time estimation by writing and reading test patterns while initializing the memories. The configuration logic writes test patterns to the memory and reads them by changing timing until the correct patterns are read. The timing information is stored and the configuration logic configures the memory controller at the end of initialization. The proposed method enables easy design of systems using PCB by solving the problem of the mismatching caused by the variation of placement and routing of components including memories and memory controllers. The proposed method can be applied to high speed SRAM, DRAM, and flash memory.