• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.2
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• pp.313-324
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• 2015

In this paper, in order to support the construction of a smart home environment of low power consumption, we propose a heterogeneous interface determination engine and architecture. Technology of "smart home" is in the spotlight according to the development of IT technology nowadays. Smart homes are configured with multiple sub-networks, and each sub-network is formed by the smart devices using various communication interfaces. Thus, in the smart home environment, interlocking technology between heterogeneous interfaces is essentially required for supporting communication between different networks. Further, each communication interface is a difference in power consumption, and home smart devices are often operated in 24 hours, especially smart phones and other wireless devices are sensitive to power consumption. Therefore, in order to build a energy efficient home network, It is important to select the appropriate interface to handle traffic depending on the situation. In this paper, we propose "The Heterogeneous Interface Decision Engine and Architecture for constructing of Low Power Home Network," and analyze the performance of the proposed method and verify the validity through experiments on the test bed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.251-265
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• 2001

As the device scaling proceeds, the operating voltage(VDD) of giga-bit DRAMs is expected to be reduced to 1.5V or down, fir improving the device reliability and reducing the power dissipation. Therefore the low-voltage circuit design techniques are required to implement giga-bit DRAMs. In this work, state-of-art low-voltage DRAM circuit techniques are reviewed, and four kinds of low-voltage circuit design techniques are newly proposed for giga-bit DRAMs. Measurement results of test chips and SPICE simulation results are presented for the newly proposed circuit design techniques, which include a hierarchical negative-voltage word-line driver with reduced subthreshold leakage current, a two-phase VBB(Back-Bias Voltage) generator, a two-phase VPP(Boosted Voltage) generator and a bandgap reference voltage generator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.11
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• pp.1214-1219
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• 2010

In this paper, a software radio system, supporting the physical layer of IEEE 802.15.4 standard, has been developed using USRP(Universal Software Radio Peripheral) board and GNU Radio package of an open source development kit for software radio. The software radio system supports the standards of BPSK and OQPSK modulations for 868/915 MHz band and OQPSK modulation for 2.45 GHz band. To verify the operation of the developed system, it has been tested under the standard signals according to the frequency band and packet structures for the transmitting and receiving operation. At 2.4 GHz, the Smart RF EV board and CC2430 modules are used to check the proper operation of the software radio system. The system performance test shows that the emission power spectrum, the eye-pattern, and PER(Packet Error Rate) meet the standard. It has been confirmed that the developed system supports the PHY layer of IEEE 802.15.4.

• Journal of Advanced Marine Engineering and Technology
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• v.41 no.4
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• pp.353-361
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• 2017

As ship-based tourism increases, safe sailing and management are necessary to prevent maritime accidents. Because external rescue support cannot arrive rapidly in the case of ship-related accidents, the initial response is very important for damage minimization. Further, for secondary damage prevention, it is necessary to accurately determine passenger positions. In this paper, considering the characteristics of a ship, the enhanced-Zigbee(e-Zigbee) position determination technology (PDT) is applied, which improved upon the Zigbee PDT by having advantages such as low power consumption and smaller size. According to user needs, a low-cost and high-precision passenger positioning tag and access point(AP) is provided. A ship testbed that yields improved positioning accuracy based on a performance evaluation is constructed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.2
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• pp.230-238
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• 2022

Internet of Things(IoT) is a communication technology that collects information of object remotely and controls the function of object by adding a communication function to object that does not have a communication function. For the IoT, various communication technologies such as Wi-Fi, 3GPP, and Bluetooth are available, and Long Range(LoRa) is communication technologies specialized in the IoT concept. LoRa is a communication technology that support long-distance, low-power, and low-speed communication, and is suitable for collecting information generated form object in remote equipment and controlling equipment. Because of these characteristics, it is used in many application field, and various performance improvement studies are in progress. This paper intends to propose an ultra-long-range LoRa communication module that can be used in a wider range of applications. We design and implement hardware, firmware, and application software for testing to develop ultra-long-range LoRa communication modules. The implemented module will be tested in a real environment to verify its performance and to check its utilization.

• KIISE Transactions on Computing Practices
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• v.24 no.2
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• pp.67-76
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• 2018

BLE (Bluetooth Low Energy) has been extensively used for communication between mobile applications and wearable devices in IoT (Internet of Things). In developing Android applications, wearable devices, on which the applications can run, should be available because the existing Android SDK does not support any BLE emulation facility. In this study, we have designed and implemented the first Android BLE emulator. Using this, we are able to develop and test BLE-based Android applications even when without wearable devices. We have also proposed an automatic generation method of Android BLE scenarios based on graph model. We have shown that the method is useful for systematically testing BLE application protocols by running the generated scenarios on the Android BLE emulator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.38-46
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• 2006

A parallel analog Viterbi decoder which decodes PRML signal of DVD has been fabricated into a VLSI chip. The parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. In this paper, the analog parallel Viterbi decoding technology is applied for the PRML signal decoding of DVD. The benefits are low power consumption and less silicon consumption. The designed circuits are analysed and the test results of the fabricated chip are reported.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.6
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• pp.568-574
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• 2020

In this paper, we propose a method to reduce the square root computation having high computation complexity in Canny edge detection algorithm using image processing. The proposed method is to reduce the number of operation calculating gradient magnitude using pixel's continuity using make a specific pattern instead of square root computation in gradient magnitude calculating operation. Using various test images and changing number of hole pixels, we can check for calculate match rate about 97% for one hole, and 94%, 90%, 88% when the number of hole is increased and measure decreasing computation time about 0.2ms for one hole, and 0.398ms, 0.6ms, 0.8ms when the number of hole is increased. Through this method, we expect to implement low power embedded vision system through high accuracy and a reduced operation number using two-hole pixels.