• Title/Summary/Keyword: 저전력 소비

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A Low Power 3D Graphics Accelerator Considering Both Active and Standby Modes for Mobile Devices (모바일기기의 동작모드와 대기모드를 모두 고려한 저전력 3차원 그래픽 가속기)

  • Kim, Young-Sik
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.2
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    • pp.57-64
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    • 2007
  • This paper proposed the low power texture cache for mobile 3D graphics accelerators. It is very important to reduce the leakage power in the standby mode for mobile 3D graphics accelerators and the memory access latency of texture mapping in the active mode which needs a large memory bandwidth. The proposed structure reduces the leakage power using variable threshold values of power mode transitions according to the selected texture filtering algorithms of application programs, which has the run time gain for texture mapping. In the trace driven cache simulation the proposed structure shows the best 7% performance gain to the previous MSA cache according to the new performance metric considering both normalized leakage power and run time impact.

전기동향

  • Korea Electrical Manufacturers Association
    • 전기산업
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    • v.8 no.5
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    • pp.114-120
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    • 1997
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Design and Implementation of Low-Power GUI for Real-Time Operating System (실시간 운영체제를 위한 저전력 GUI 설계 및 구현)

  • Jeong, Jae-Yeop;Lee, Cheol-Hoon
    • Proceedings of the Korea Contents Association Conference
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    • 2007.11a
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    • pp.817-821
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    • 2007
  • A technique which uses the energy for a long time have been recognized as a important problem in embedded system with restricted battery. Recently the energy consumption is increased by using a large size of TFT-LCD and touch screen in embedded system. In this paper, we studied the frame buffer monitoring which can be reduced an energy consumption in GUI. The frame buffer monitoring technique is the energy degrade plan which adjusts Refresh-rate and Backlight. The technique must guarantee the quality of screen.

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A Development of Home Gateway System supporting Standby Power (대기전력 지원 홈게이트웨이 시스템 개발)

  • Cho, Soo-Hyung;Lee, Sang-Hak;Kim, Dae-Hwan
    • Proceedings of the Korean Information Science Society Conference
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    • 2010.06d
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    • pp.432-435
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    • 2010
  • 네트워크 기기분야에서는 정보통신기기 및 고속 멀티미디어 데이터 수요의 증가에 따라 네트워크 기기의 전력소비가 꾸준히 증가하고 있다. 특히 홈 네트워크 기기들은 전원이 연결되어 있는 상태로 동작하여 데이터 통신이 발생하지 않는 상황에서도 일정한 전력소모가 발생하므로 이에 대한 대처기술이 마련되어야 한다. 본 논문에서 대기전력 지원 홈게이트웨이 시스템 구현을 위하여 하드웨어를 설계하고 저전력 대기모드 지원 네트워크 프로토콜 인터페이스 개발하였으며 홈게이트웨이 시뮬레이터 S/W를 개발하여 홈게이트웨이의 기능을 시험테스트 하였다. 시뮬레이터 시험결과 각 네트워크 포트에서 발생된 트래픽에 따라 홈게이트웨이의 전원 모드가 변경됨을 확인할 수 있었으며 대기모드 시 소모 전력이 1W 미안으로 측정되었다.

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Design of a Low Power MictoController Core for Intellectual Property applications (IP활용에 적합한 저전력 MCU CORE 설계)

  • Lee, Kwang-Youb;Lee, Dong-Yup
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.2
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    • pp.470-476
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    • 2000
  • This paper describes an IP design of a low-power microcontroller using an architecture level design methodology instead of a transistor level. To reduce switching capacitance, the register-toregister data transfer is adopted to frequently used register transfer micro-operations. Also, distributed buffers are proposed to reduce a input data rising edge time. To reduce power consumption without any loss of performance, pipeline processing should be used. In this paper, a 4-stage pipelined datapath being able to process CISC instructions is designed. Designed microcontroller lessens power consumption by 20%. To measure a power consumption, the SYNOPSYS EPIC powermill is used.

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OCP Cold Storage Test-bed (OCP Cold Storage 테스트베드)

  • Lee, Jaemyoun;Kang, Kyungtae
    • KIISE Transactions on Computing Practices
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    • v.22 no.3
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    • pp.151-156
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    • 2016
  • Cloud computing systems require a huge number of storage servers due to the growing implications of power bills, carbon emissions, and logistics of data centers. These considerations have motivated researchers to improve the energy efficiency of storage servers. Most servers use a lot of power irrespective of the amount of computing that they are doing, and one important goal is to redesign servers to be power-proportional. However, Research on large-scale storage systems is hampered by their cost. It is therefore desirable to develop a scalable test-bed for evaluating the power consumption of large-scale storage systems. We are building on open-source projects to construct a test-bed which will contribute to the assessment of power consumption in tiered storage systems. Integrating the cloud application platform can easily extend the proposed testbed laying a foundation for the design and evaluation of low-power storage servers.

Gender Classification System Based on Deep Learning in Low Power Embedded Board (저전력 임베디드 보드 환경에서의 딥 러닝 기반 성별인식 시스템 구현)

  • Jeong, Hyunwook;Kim, Dae Hoe;Baddar, Wisam J.;Ro, Yong Man
    • KIPS Transactions on Software and Data Engineering
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    • v.6 no.1
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    • pp.37-44
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    • 2017
  • While IoT (Internet of Things) industry has been spreading, it becomes very important for object to recognize user's information by itself without any control. Above all, gender (male, female) is dominant factor to analyze user's information on account of social and biological difference between male and female. However since each gender consists of diverse face feature, face-based gender classification research is still in challengeable research field. Also to apply gender classification system to IoT, size of device should be reduced and device should be operated with low power. Consequently, To port the function that can classify gender in real-world, this paper contributes two things. The first one is new gender classification algorithm based on deep learning and the second one is to implement real-time gender classification system in embedded board operated by low power. In our experiment, we measured frame per second for gender classification processing and power consumption in PC circumstance and mobile GPU circumstance. Therefore we verified that gender classification system based on deep learning works well with low power in mobile GPU circumstance comparing to in PC circumstance.

Performance Analysis of the Underwater Acoustic Communication with Low Power Consumption by Sea Trials (해상실험을 통한 저전력 수중음향통신 기법의 성능 분석)

  • Lee, Tae-Jin;Kim, Ki-Man
    • Journal of Navigation and Port Research
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    • v.35 no.10
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    • pp.811-816
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    • 2011
  • In this paper, we analysis to consider the performance of PSPM (Phase Shift Pulse-position Modulation), the one of the low power communication technique, in near-field underwater sound channel by sea trial. PSPM is a QPSK(Quadrature Phase Shift Keying) modulation combined with PPM(Pulse Position Modulation) for low power communication in WBAN(Wireless Body Area Network). It is known that the bandwidth efficiency of PSPM is lower than conventional PSK but the power efficiency increases. In this paper, we will analyze the BER performance of PSPM using data acquired from the sea trials. The BER of QPSK was $6.04{\times}10^{-2}$, PSPM was $3.5{\times}10^{-1}$. Also, PSNR of QPSK was 9.37 dB and in case of PSPM was 9.11 dB.

Authentication for Beacon Service (비콘 서비스를 위한 보안 인증 방법)

  • Oh, Jeong-Gyu;Sin, Ji-Seon;Kim, Hyung-Seok
    • Proceedings of the Korea Information Processing Society Conference
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    • 2016.10a
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    • pp.793-796
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    • 2016
  • 정보통신 기술의 발달로 사물인터넷에 대한 관심이 증가하였다. 사물인터넷의 한 요소인 무선 큰거리 통신 기술에는 WIFi, 블루투스, ZigBee 등이 있다. 이러한 기술들 중 저전력 블루투스는 낮은 전력 소비와 범용성 덕분에 많은 각광을 밭고 있다. BLE(Bluetooth LE)의 한 형태인 비콘은 더욱 저전력이며, 패킷을 전달하는 방식 또한 기존의 블루투스와 차이가 있다. 본 논문에서논 컨텐츠 보안이 필요한 비콘 서비스의 예시로 비콘을 통한 새로운 형태의 음악 음반을 제시하였다. 또한, 그 보안 특성에 맞춰 패킷 이중화, RSSI, Serial Number Binding 등의 기술들을 사용한 보안 방법을 설계 및 구현한 보안 사레에 대하여 서술한다.

Design of UWB CMOS Low Noise Amplifier Using Inductor Peaking Technique (인덕터 피킹기법을 이용한 초광대역 CMOS 저잡음 증폭기 설계)

  • Sung, Young-Kyu;Yoon, Kyung-Sik
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.1
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    • pp.158-165
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    • 2013
  • In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in $0.18-{\mu}m$ CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.