• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.853-855
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• 2009

센서 노드를 위한 운영체제는 제한된 시스템 자원 하에서 동작하므로 전력 소모량을 최소화 시킬 수 있는 시스템 레벨의 저전력 기법과 함께 실시간성을 지원해야 한다. 이에 본 논문에서는 저전력 마이크로프로세서인 ATmega128L 기반의 센서 노드 하드웨어 플랫폼을 설계하고, 센서노드 플랫폼에서 동작하는 멀티스레드 기반의 실시간 운영체제인 RT-UNOS를 개발하였다. 제안한 센서 노드 플랫폼의 동작 검증을 위하여 기존의 센서노드용 운영체제인 TinyOS와 MANTIS, cc-EDF와의 성능을 구현한 센서노드 상에서 실험을 진행하여 비교 분석하였다.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.31-39
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• 2013

In this paper, we propose a power-efficient scheduling scheme that stochastically minimizes the power consumption of a real-time parallel task while meeting the deadline on multicore processors. The proposed scheme applies the parallel processing that executes a task on multiple cores concurrently, and activates a part of all available cores with unused cores powered off, in order to save power consumption. It is proved that the proposed scheme minimizes the mean power consumption of a real-time parallel task with probabilistic computation amount on DVFS-enabled multicore processors with a finite set of discrete clock frequencies. Evaluation shows that the proposed scheme saves up to 81% power consumption of the previous method.

• Journal of Internet of Things and Convergence
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• v.8 no.4
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• pp.1-7
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• 2022

As the number of IoT devices increases, power management of the cluster head, which acts as a gateway between the cluster and sink nodes in the IoT network, becomes crucial. Particularly when the cluster head is a mobile wireless terminal, the power consumption of the IoT network must be minimized over its lifetime. In addition, the delay of information transmission in the IoT network is one of the primary metrics for rapid information collecting in the IoT network. In this paper, we propose a low-power buffer management algorithm that takes into account the information transmission delay in an IoT network. By forwarding or skipping received packets utilizing deep Q learning employed in deep reinforcement learning methods, the suggested method is able to reduce power consumption while decreasing transmission delay level. The proposed approach is demonstrated to reduce power consumption and to improve delay relative to the existing buffer management technique used as a comparison in slotted ALOHA protocol.

• Journal of KIISE:Information Networking
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• v.30 no.2
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• pp.179-188
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• 2003

Advances in wireless networking technology has engendered a new paradigm of computing, called mobile computing, in which users carrying portable devices have access to a shared infrastructure independent of their physical locations. Wireless communication has some restraints such as disconnection, low bandwidth, a variation of available bandwidth, network heterogeneity, security risk, small storage, and low power. Power adaptation routing scheme overcome the shortage of power by adjusting the output power, was proposed. Existing power saving routing algorithm has some minor effect such as seceding from shortest path to minimize the power consumption, and number of nodes that Participate in routing than optimal because it select a next node with considering only consuming power. This paper supplements the weak point in the existing power saving routing algorithm as considering the gradual approach to final destination and the number of optimal nodes that participate in routing.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.6
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• pp.141-145
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• 2021

Various types of memory architectures have been developed, and various compiler optimization techniques have been studied to efficiently use them. In particular, since a memory is a major component that determines performance in mobile computing devices, various optimization techniques have been developed to support them. Recently, a lot of research on hybrid type memory architecture is being conducted, so various compiler techniques are being studied to support it. Existing compiler optimization techniques can be used to achieve the required minimum performance and constraint on low power according to market requirements. References for determining the low-power effect and the degree of performance improvement using these optimization techniques are not properly provided yet. This study was conducted to provide the experimental results of the existing compiler technique as a reference for the development of multibank memory architecture.

• Proceedings of the KIEE Conference
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• summer
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• pp.168-170
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• 2004

현대의 전력회사들은 전력계통의 현재 운용상황을 파악하기 위하여 상태추정을 사용한다. 상태추정기는 계통 내 각 지점에서 측정된 전력이나 전압, 전류등의 데이터를 이용하여 반복연산을 수행함으로써 전력계통의 상태(voltage profile)를 추정한다. 이때, 모든 데이터는 동시에 측정이 되었다는 가정 하에 상태추정 연산에 이용되지만, 실제로 모든 데이터 측정의 동기성을 확보하는 것은 사실상 불가능하다. 최근 인공위성에 의해 동기화된 페이저 측정장치가 전력계통 운용에 사용되고 있으며 본 논문에서는 이렇게 이미 이용 가능한 페이저 측정 데이터를 상태추정에 이용하는 방법을 시도하였다. 위성에 의해 동기화된 페이저 측정데이터는 데이터 측정의 동기성 확보뿐만 아니라, 데이터의 정밀도 및 위상각의 직접적인 측정이라는 둥의 여러 가지 면에서 매우 효용성이 높은 데이터이다. 본 연구를 통해 개발된상태추정 프로그램은 IEEE 14모선 시험계통을 이용하여 그 타당성을 검증하였다.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.241-251
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• 2007

Energy consumption in the instruction cacheaccounts for a significant portion of the total processor energy consumption. Therefore, reducing energy consumption in the instruction cache is important in designing embedded processors. This paper proposes a method for reducing dynamic energy consumption in the instruction cache by partitioning it to smaller (less energy-consuming) sub-caches. When a request comes into the proposed cache, only one sub-cache is accessed by utilizing the locality of applications. By contrast, the other sub-caches are not accessed, leading todynamic energy reduction. In addition, the proposed cache reduces dynamic energy consumption by eliminating the energy consumed in tag matching. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar. with power parameters obtained from CACTI. Simulation results show that the proposed cache reduces dynamic energy consumption by $37%{\sim}60%$ compared to the traditional direct-mapped instruction cache.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.473-474
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• 2007

본 연구는 체내 이식형 Pacemaker를 연구하면서 심장 질환을 Therapy 해 주는 방법에 대해 저전력 및 성능향상에 중점을 두고 연구 및 실험을 하였다. 우선적으로 심장의 심박동을 연산량이 적은 Peak_detection에서 체크하여 전력소모를 줄이고 나오는 각 심실 및 심방의 Interval을 Disease_episode 에서 받는다. 여기서 5가지 심실 및 심방에 관한 질환들 (VF : Ventricular Fibrillation, VT : Ventricular Tachycardia, FVT : Fast Ventricular Tachycardia, FAT_AF : Fast Atrial Tachycardia/Atrial Fibrillation, AT_AF : Atrial Tachycardia AT_AF : Atrial Fibrillation)을 판별한 후 각 병증에 맞는 Therapy 값을 출력하게 하였다. 그 외에 남아있는 병증에 대해서도 Therapy가 저전력 및 성능향상 되도록 설계하였다. 기존에 적용되어 있는 Detection 기법에서는 각각의 병증에 대해서 각 Detection이 있어 VF와 VT 사이에 있는 FVT와 같은 병증을 치료할 때 FVT 같은 경우에는 VF와 VT사이에 있는 질병이기 때문에 FVT_VF 및 FVT_VT와 같이 각각의 Detection을 두어 전력 소모가 있었다. 심장에서는 여러 질병이 한번에 나을 수 없다는 것에 착안하여 (심박동 Interval에 의해 질병이 판단되므로) 다른 병증이지만 같은 진단 기준을 쓰는 Detection을 통합함으로써 하나의 모듈로 구성하여 Gate수를 줄이고 저전력을 구현하였다. 또한 병증을 판별하는 진단 기준 모듈 중 Onset_Criterion 재설계하여 좀더 성능 향상에 중점을 두었다.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.20 no.10
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• pp.21-28
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• 2002

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.22 no.12
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• pp.21-30
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• 2004