• Title/Summary/Keyword: 자원 레벨링

Search Result 23, Processing Time 0.028 seconds

Real-Time Link Throughput Management Algorithms for Generalized PF Scheduling in Wireless Mobile Networks (무선이동 네트워크에서 일반화된 PF 스케줄링을 위한 실시간 링크 용량 관리 알고리즘)

  • Joung, Hee-Jin;Mun, Cheol;Yook, Jong-Gwan
    • Journal of Internet Computing and Services
    • /
    • v.12 no.5
    • /
    • pp.1-9
    • /
    • 2011
  • Wireless mobile networks that exploit generalized PF scheduling can dynamically allocate network resources by using scheduling parameters. There are limitations to predict throughputs by the conventional stochastic approach in general. Moreover the limitations make it difficult to find appropriate scheduling parameters for achieving the demanded throughputs. This paper derives a prediction algorithm that predicts throughputs of the networks by using deterministic approach. A throughput adjust algorithm and a throughput switching algorithm are derived from the prediction algorithm. The performance of the throughput prediction/switching algorithms is evaluated by a simulator based on IEEE 802.16m system.

The Design and Implementation of 3[kW] Sollar Cell PWM Inverter (3[kW]급 태양광 인버터의 설계 및 구현)

  • Song, Y.U.;Oh, S.C.
    • Proceedings of the KIPE Conference
    • /
    • 2008.06a
    • /
    • pp.75-77
    • /
    • 2008
  • 석유를 포함한 자원고갈과 지구온난화와 같은 환경문제로 인하여 자연에너지를 이용한 소규모 태양광발전이 각광을 받고 있다. 본 논문에서는 web상에서 모니터링이 가능한 3[kW]급 태양광 발전 인버터의 설계 및 구현방법을 제시한다. 설계된 인버터는 독립형이며, Boost Converter를 이용하여 350[Vdc]를 400[Vdc]로 승압한 이후 SPWM 방식을 이용하여 교류 파형을 얻어낸다. LC 필터를 통과한 출력파형은 실효치 220[Vac], 주파수는 60[Hz]의 상용전원이고, THD는 5% 이하이다. 또한 350[Vdc]의 10% 레벨에서는 Boost Converter의 Duty를 자동 조정하여 출력단의 전압을 400[Vdc]로 유지할 수 있는 기능을 포함한다. 또한, 출력단의 전압과 전류를 센싱한 후, PC에서의 모니터링 시스템을 구축하였다. 이를 통해 인버터에 포함된 PC를 서버로 활용하여, LAN이 가능한 곳에서는 인버터의 상태와 발전량을 알 수 있다.

  • PDF

Performance Control of the Capacitated Re-entrant Line using Genetic Approach (유전자 알고리즘을 이용한 유한용량 재진입 라인 성능 제어)

  • Choi, Jin-Young
    • Journal of Korean Society of Industrial and Systems Engineering
    • /
    • v.31 no.4
    • /
    • pp.106-113
    • /
    • 2008
  • 본 논문에서는 유한용량 재진입 생산라인에서의 스케줄링 문제에 대한 유전자적 접근 방법을 제안하였다. 알고리즘에서 사용되는 염색체의 구조는 워크스테이션의 버퍼레벨에 대한 모든 가능한 경우를 고려하여 정의되었으며, 염색체의 각 유전자에는 그에 대응되는 시스템 상태에서 우선 순위를 갖는 작업 단계의 값이 할당되도록 하였다. 또한, 제안된 알고리즘의 구현 방법으로서 워크스테이션의 버퍼와 프로세싱 자원을 할당할 때 작업 간 우선 순위를 고려하는 동시에 각 워크스테이션의 로컬 유휴 상태를 지양하는 우선순위 기반 랜덤화 정책 알고리즘을 제안하였다. 실험을 통하여 제안된 알고리즘의 성능을 평가하였으며, 기존에 무한용량 재진입 생산라인 스케줄링 문제에 많이 이용되었던 휴리스틱과 비교하여 보다 효율적임을 보였다.

Implementation of Secured SMTP Gateway (SMTP 보안 게이트웨이의 구현)

  • Min, Zee-Young;Kim, Hyun-Koo;Chang, Beom-Hwan;Chung, Tae-Myung
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2002.11b
    • /
    • pp.937-940
    • /
    • 2002
  • 인터넷의 확산과 더불어 전자 우편의 사용이 크게 늘면서 스팸메일의 심각성이 대두되고 있다. 현재 스팸메일을 막기 위한 여러 가지 기법이 제안되고 있으나, 대부분의 방법이 메일 서버내의 정책에 따른 메일 필터링으로, 스팸메일로 인해 네트워크 자원이 소실되는 문제는 여전히 해결되지 않고 있다. 또한 여러 메일 서버가 같은 내용의 메일로 반복적으로 공격을 당하게 된다. 본 논문에서는 게이트웨이 수준에서의 메일감시를 통하여 불필요한 스팸메일로부터 네트워크 자원을 보호하고, 내부 메일 서버 전체를 보호 할 수 있는 시스템에 대해 논의 해보고자 한다. 커널 레벨에서의 패킷 감시로 속도가 빠르고, 또한 가상의 커넥션을 맺어 게이트웨이에서 메일을 완전히 받은 후 검사하므로 더욱더 다양한 정책으로 SMTP를 감시할 수 있으며, 이 시스템은 IP 기반의 다른 프로토콜이나 타 서비스로의 응용 또한 기대할 수 있다.

  • PDF

A Novel Cooperative Warp and Thread Block Scheduling Technique for Improving the GPGPU Resource Utilization (GPGPU 자원 활용 개선을 위한 블록 지연시간 기반 워프 스케줄링 기법)

  • Thuan, Do Cong;Choi, Yong;Kim, Jong Myon;Kim, Cheol Hong
    • KIPS Transactions on Computer and Communication Systems
    • /
    • v.6 no.5
    • /
    • pp.219-230
    • /
    • 2017
  • General-Purpose Graphics Processing Units (GPGPUs) build massively parallel architecture and apply multithreading technology to explore parallelism. By using programming models like CUDA, and OpenCL, GPGPUs are becoming the best in exploiting plentiful thread-level parallelism caused by parallel applications. Unfortunately, modern GPGPU cannot efficiently utilize its available hardware resources for numerous general-purpose applications. One of the primary reasons is the inefficiency of existing warp/thread block schedulers in hiding long latency instructions, resulting in lost opportunity to improve the performance. This paper studies the effects of hardware thread scheduling policy on GPGPU performance. We propose a novel warp scheduling policy that can alleviate the drawbacks of the traditional round-robin policy. The proposed warp scheduler first classifies the warps of a thread block into two groups, warps with long latency and warps with short latency and then schedules the warps with long latency before the warps with short latency. Furthermore, to support the proposed warp scheduler, we also propose a supplemental technique that can dynamically reduce the number of streaming multiprocessors to which will be assigned thread blocks when encountering a high contention degree at the memory and interconnection network. Based on our experiments on a 15-streaming multiprocessor GPGPU platform, the proposed warp scheduling policy provides an average IPC improvement of 7.5% over the baseline round-robin warp scheduling policy. This paper also shows that the GPGPU performance can be improved by approximately 8.9% on average when the two proposed techniques are combined.

A Design of The PHB Mapping Model for Combining Services with DiffServ in The MPLS Network (멀티 프로토콜 레벨 스위칭망에서 DiffServ와의 서비스 결합을 위한 PHB 매핑모델 설계)

  • Moon, Suk-Hwa;Lee, Sung-Hwa
    • The Journal of the Institute of Internet, Broadcasting and Communication
    • /
    • v.11 no.2
    • /
    • pp.127-133
    • /
    • 2011
  • This study proposed the PHB mapping model for combining services with DiffServ in the MPLS network capable of high-speed switching, and the effective differential bandwidth service model in the MPLS network on the basis of the proposed mapping model. The result of simulation on the service model using PRI showed that the transmission rate was achieved as much as the assigned bandwidth regardless of the increase of traffic as far as the EF PHB did not exceed the assigned bandwidth at the peak rate when the overall traffic increased.

Deterministic Real-Time Task Scheduling (시간 결정성을 보장하는 실시간 태스크 스케줄링)

  • Cho, Moon-Haeng;Lee, Soong-Yeol;Lee, Won-Yong;Jeong, Geun-Jae;Kim, Yong-Hee;Lee, Cheol-Hoon
    • The Journal of the Korea Contents Association
    • /
    • v.7 no.1
    • /
    • pp.73-82
    • /
    • 2007
  • In recent years, embedded systems have been expanding their application domains from traditional applications (such as defense, robots, and artificial satellites) to portable devices which execute more complicated applications such as cellular phones, digital camcoders, PMPs, and MP3 players. So as to manage restricted hardware resources efficiently and to guarantee both temporal and logical correctness, every embedded system use a real-time operating system (RTOS). Only when the RTOS makes kernel services deterministic in time by specifying how long each service call will take to execute, application programers can write predictable applications. Moreover, so as for an RTOS to be deterministic, its scheduling and context switch overhead should also be predictable. In this paper, we present the complete generalized algorithm to determine the highest priority in the ready list with 22r levels of priorities in a constant time without additional memory overhead.

Fixed IP-port based Application-Level Internet Traffic Classification (고정 IP-port 기반 응용 레벨 인터넷 트래픽 분석에 관한 연구)

  • Yoon, Sung-Ho;Park, Jun-Sang;Park, Jin-Wan;Lee, Sang-Woo;Kim, Myung-Sup
    • The KIPS Transactions:PartC
    • /
    • v.17C no.2
    • /
    • pp.205-214
    • /
    • 2010
  • As network traffic is dramatically increasing due to the popularization of Internet, the need for application traffic classification becomes important for the effective use of network resources. In this paper, we present an application traffic classification method based on fixed IP-port information. A fixed IP-port is a {IP address, port number, transport protocol}triple dedicated to only one application, which is automatically collected from the behavior analysis of individual applications. We can classify the Internet traffic more accurately and quickly by simple packet header matching to the collected fixed IP-port information. Therefore, we can construct a lightweight, fast, and accurate real-time traffic classification system than other classification method. In this paper we propose a novel algorithm to extract the fixed IP-port information and the system architecture. Also we prove the feasibility and applicability of our proposed method by an acceptable experimental result.

Design and Analysis of Technical Management System of Personal Information Security using Web Crawer (웹 크롤러를 이용한 개인정보보호의 기술적 관리 체계 설계와 해석)

  • Park, In-pyo;Jeon, Sang-june;Kim, Jeong-ho
    • Journal of Platform Technology
    • /
    • v.6 no.4
    • /
    • pp.69-77
    • /
    • 2018
  • In the case of personal information files containing personal information, there is insufficient awareness of personal information protection in end-point areas such as personal computers, smart terminals, and personal storage devices. In this study, we use Diffie-Hellman method to securely retrieve personal information files generated by web crawler. We designed SEED and ARIA using hybrid slicing to protect against attack on personal information file. The encryption performance of the personal information file collected by the Web crawling method is compared with the encryption decryption rate according to the key generation and the encryption decryption sharing according to the user key level. The simulation was performed on the personal information file delivered to the external agency transmission process. As a result, we compared the performance of existing methods and found that the detection rate is improved by 4.64 times and the information protection rate is improved by 18.3%.

A New Resource Allocation Algorithm of Functional Units to Minimize Power Dissipation (전력소비 최소화를 위한 새로운 펑션유닛의 자원 할당 알고리듬)

  • Lin, Chi-Ho
    • Journal of IKEEE
    • /
    • v.8 no.2 s.15
    • /
    • pp.181-185
    • /
    • 2004
  • This paper reduces power dissipation with the minimum switching activity of functional units that have many operators. Therefore, it has more effects of power dissipation that operator dissipation to reduce power dissipation of whole circuit preferentially. This paper proposes an algorithm that minimize power dissipation in functional units operations that affect much as power dissipation in VLSI circuit. The algorithm has scheduled operands using power library that has information of all operands. The power library upgrades information of input data in each control step about all inputs of functional units and the information is used at scheduling process. Therefore, the power dissipation is minimized by functional units inputs in optimized data. This paper has applied algorithm that proposed for minimizing power dissipation to functional unit in high level synthesis. The result of experiment has effect of maximum 9.4 % for minimizing power dissipation.

  • PDF