• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.62-71
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• 2001

This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on Altera Flex EPF10KGC503-3 FPGA chip in real-time mode, and performed successfully.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.217-225
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• 2005

This paper presents specialized DSP instructions and their architecture for the Viterbi algorithm used in various wireless communication standards. The proposed architecture can significantly reduce the Trace Back (TB) latency. The proposed instructions perform the Add Compare Select (ACS) and TB operations in parallel and the architecture has special hardware, called the Offset Calculation Unit (OCU), which automatically calculates data addresses for the trellis butterfly computations. Logic synthesis has been Performed using the Samsung SEC 0.18 μm standard cell library. OCU consists of 1,460 gates and the maximum delay of OCU is about 5.75 ns. The BER performance of the ACS-TB parallel method increases about 0.00022dB at 6dB Eb/No compared with the typical TB method, which is negligible. When the constraint length K is 5, the proposed DSP architecture can reduce the decoding cycles about 17% compared with the Carmel DSP and about 45% compared with 7MS320c15x.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.2
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• pp.165-182
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• 2001

In this paper, we describe a design and implementation of the Wireless Markup Language(WML) compiler to deploy wireless Internet services effectively. The WML compiler translates textual WML decks into binary ones in order to reduce the traffic on wireless links that have relatively low bandwidth to wireline links and mitigate the processing overhead of WML decks on, wireless terminals that have relatively low processing power to fixed workstations. In addition, it takes over the overhead of eXtensible Markup Language(XML) well-formedness and validation processes. The WML compiler consists of the lexical analyzer and parser modules. The granunar for the WML parser module is LALR(1) context-free grammar that is designed based on XML 1.0 and WML 1.2 DTD(Document Type Definition) with the consideration of the Wireless Application Protocol Binary XML grammar. The grammar description is converted into a C program to parse that grammar by using parser generator. Even though the tags in WML will be extended or WML DTD will be upgraded, this approach has the advantage of flexibility because the program is generated by modifying just the changed parts. We have verified the functionality of the WML compiler by using a WML decompiler in the public domain and by using the Nokia WAP Toolkit as a WAP client. To measurethe compressibility gain of the WML compiler, we have tested a large number of textual WML decks and obtained a maximum 85 %. As the effect of compression is reduced when the portion of general textual strings increases relative to one of the tags and attributes in a WML deck, an extended encoding method might be needed for specific applications such as compiling of the WML decks to which the Hyper Text Markup Language document is translated dynamically.

• Journal of Navigation and Port Research
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• v.28 no.3
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• pp.213-219
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• 2004

In this paper, a LNA(Low Noise Amplifier) has been developed, which is operating at L-band i.e., 1452∼1492 MHz for satellite DAB(Digital Audio Brcadcasting) receiver. The LNA is designed to improve input and output reflection coefficient and VSWR(Voltage Standing Wave Ratio) by balanced amplifier. The LNA consists of low noise amplification stage and gain amplification stage, which make a using of GaAs FET ATF-10136 and VNA-25 respectively, and is fabricated by hybrid method. To supply most suitable voltage and current, active bias circuit is designed Active biasing offers the advantage that variations in $V_P$ and $I_{DSS}$ will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets $V_{gs}$ for the desired drain voltage and drain current. The LNA is fabricated on FR-4 substrate with RF circuit and bias circuit, and integrated in aluminum housing. As a reults, the characteristics of the LNA implemented more than 32 dB in gain. 0.2 dB in gain flatness. lower than 0.95 dB in noise figure, 1.28 and 1.43 each input and output VSWR, and -13 dBm in $P_{1dB}$.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.4
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• pp.244-254
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• 2009

This paper describes a remote system to monitor the circadian behavioral patterns of elders who live alone. The proposed system was designed and implemented to provide more conveniently and reliably the required functionalities of a remote monitoring system for elders based on the development of first phase prototype[2]. The developed system is composed of an in-house sensing system and a server system. The in-house sensing system is a set of wireless sensor nodes which have pyroelectric infrared (PIR) sensor to detect a motion of elder. Each sensing node sends its detection signal to a home gateway via wireless link. The home gateway stores the received signals into a remote database. The server system is composed of a database server and a web server, which provides web-based monitoring system to caregivers (friends, family and social workers) for more cost effective intelligent care service. The improved second phase system can provide 'automatic diagnosis', 'going out detection', and enhanced user interface functionalities. We have evaluated the first and second phase monitoring systems from real field experiments of 3/4 months continuous operation with installation of 9/15 elders' houses, respectively. The experimental results show the promising possibilities to estimate the behavioral patterns and the current status of elder even though the simplicity of sensing capability.

• The KIPS Transactions:PartA
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• v.10A no.5
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• pp.469-478
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• 2003

Internet information search engines using web robots visit servers conneted to the Internet periodically or non-periodically. They extract and classify data collected according to their own method and construct their database, which are the basis of web information search engines. There procedure are repeated very frequently on the Web. Many search engine sites operate this processing strategically to become popular interneet portal sites which provede users ways how to information on the web. Web search engine contacts to thousands of thousands web servers and maintains its existed databases and navigates to get data about newly connected web servers. But these jobs are decided and conducted by search engines. They run web robots to collect data from web servers without knowledge on the states of web servers. Each search engine issues lots of requests and receives responses from web servers. This is one cause to increase internet traffic on the web. If each web server notify web robots about summary on its public documents and then each web robot runs collecting operations using this summary to the corresponding documents on the web servers, the unnecessary internet traffic is eliminated and also the accuracy of data on search engines will become higher. And the processing overhead concerned with web related jobs on web servers and search engines will become lower. In this paper, a monitoring system on the web server is designed and implemented, which monitors states of documents on the web server and summarizes changes of modified documents and sends the summary information to web robots which want to get documents from the web server. And an efficient web robot on the web search engine is also designed and implemented, which uses the notified summary and gets corresponding documents from the web servers and extracts index and updates its databases.