• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.40-48
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• 2015

This paper presents a processor that performs QR decomposition (QRD) as well as Lattice Reduction (LR) for multiple-input multiple-output (MIMO) systems. By sharing the operations commonly required in QRD and LR, the hardware complexity of the proposed processor is reduced significantly. In addition, the proposed processor is designed based on a multi-cycle architecture so as to reduce the hardware complexity. The proposed processor is implemented with 139k logic gates in a $0.18-{\mu}m$ CMOS process, and its latency is $5{\mu}s$ for $8{\times}8$ MIMO preprocessing both QRD and LR where the operating frequency is 117MHz.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.1
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• pp.63-72
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• 2007

Recently, as recognizing the risk about the infection of an infectious wastes, the problems about the management and treatment of the infectious wastes stand out socially. In this paper, as being possible monitoring whole processing from the origin of the infectious waste to the processing plant, using the RFID which is the kernel technology of the next generation, we tried to solve the second infection problem by inefficient treatment of the infectious wastes. Through the research suggesting in this paper, as storing and monitoring the procedural business articles and the problem about miss-writing and input error being found in management system like documentary writing by the existing manager and computation input by the web application, we can understand the management state, immediately. And the Bio information for the personal authentication is carried out through storing the feature vector calculation by the PCA algorithm, into the tag. It suggested more systematic and safer management plan than previous thing, as giving attention about the wastes to manager.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• The Transactions of the Korea Information Processing Society
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• v.2 no.4
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• pp.603-610
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• 1995

In this paper, we present a highly efficient simulation package which supports simulation from functional level to gate level. The package consists of a set of front-end tools, a logic simulator, named HSIM(Highly efficient logic SIMulator), and an waveform analyzer. The front-end tools include a netlist compiler, functional primitive compiler and behavioral compiler. Key feature of developed simulator is that the compiled behavioral models written in C language are directly executed in the simulation engine using incremental loader. By doing so, we achieved significant speed up as compared with the interpretive functional simulator. Experimental results show that HSIM runs about 55% faster than traditional unit-delay event-driven interpretive simulator.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1792-1802
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• 1996

The analysis of prepositional phrases in English-to Korean machine translation has problem on the PP-attachment resolution, semantic analysis, and acquisition of information. This paper presents an analysis system for prepositional phrases, which solves the problem. The analysis system consists of the PP-attachment resolution hybrid system, semantic analysis system, and semantic feature generator that automatically generates input information. It provides objectiveness in analyzing prepositional phrases with the automatic generation of semantic features. The semantic analysis system enables to generate natural Korean expressions through selection semantic roles of prepositional phrases. The PP-attachment resolution hybrid system has the merit of the rule-based and neural network-based method.

• Journal of Internet Computing and Services
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• v.12 no.3
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• pp.89-99
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• 2011

The payload signature-based traffic classification system has to deal with large amount of traffic data, as the number of internet-based applications and network traffic continue to grow. While a number of pattern-matching algorithms have been proposed to improve processing speedin the literature, the performance of pattern matching algorithms is restrictive and depends on the features of its input data. In this paper, we studied how to optimize the search space in order to improve the processing speed of the payload signature-based traffic classification system. Also, the feasibility of our design choices was proved via experimental evaluation on our campus traffic trace.

• The Journal of the Korea Contents Association
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• v.9 no.1
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• pp.159-166
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• 2009

In this paper, we analyse the noise robustness of MLPs(Multilayer perceptrons) through deriving the probability density function(p.d.f.) of output nodes with additive input noises and the misclassification ratio with the integral form of the p.d.f. functions. Also, we propose linear preprocessing methods to improve the noise robustness. As a preprocessing stage of MLPs, we consider ICA(independent component analysis) and PCA(principle component analysis). After analyzing the noise reduction effect using PCA or ICA in the viewpoints of SNR(Singal-to-Noise Ratio), we verify the preprocessing effects through the simulations of handwritten-digit recognition problems.

• The Transactions of the Korea Information Processing Society
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• v.3 no.2
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• pp.225-230
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• 1996

We propose a statistical test for the nonlinear combiner logics which are usually combined with two maximal Linear Feedback Shift Registers and generate pseudorandom bit sequences. This test uses the mutual information between the output and set of inputs which will be a random variable and its distribution is obeyed to an approximate $\{chi}^2$ -distribution. We adopt this statistic to a $\{chi}^2$ -test of independence by using contingency table. We also apply a proposed test to some non-linear crptosystems and show that this useful to evaluate the strength of the cryptosystems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.6
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• pp.1114-1116
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• 2015

In this paper, we propose a load distribution scheme in SDN utilizing load redirection, enabling incoming messages to be migrated to another controller. Specifically, when the capacity of a controller reaches a threshold, the controller makes incoming packets be migrated to a less-loaded controller to prevent them from being blocked. Analytical result shows that our scheme has lower blocking probability than the conventional scheme.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.10
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• pp.78-88
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• 1990

To evaluate the performance of a multiprocessor system, a discrete event model of memory interference in the system employing multiple-bus interconnection networks is proposed. An analytic model of the system is presented and then simulator models are implemented for cross-verifying the analytic results and simulation results. The simulator model takes as input the number of processors, the number of memory modules, the number of buses and the local memory miss ratio. The model produces as output the memory bandwidth, the processor, memory module and bus utilization and the bus contention ratio. Using the model in the design of the system, it is possible to evaluate the system performance by analyzing the interaction of the input parameters.