• Journal of Korea Multimedia Society
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• v.14 no.7
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• pp.917-923
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• 2011

In this paper, a new prediction based embedded compression (EC) codec algorithm for the JPEG2000 encoder system is proposed to reduce excessive memory requirements. The EC technique can reduce the 50 % memory requirement for intermediate low-frequency coefficients during multiple discrete wavelet transform (DWT) stages compared with direct implementation of the DWT engine of this paper. The LOCO-I predictor and MAP are widely used in many lossless picture compression codec. The proposed EC algorithm use these predictor which are very simple but surprisingly effective. The predictive EC scheme adopts a forward adaptive quantization and fixed length coding to encoding the prediction error. Simulation results show that our LOCO-I and MAP based EC codecs present only PSNR degradation of 0.48 and 0.26 dB in average, respectively. The proposed algorithm improves the average PSNR by 1.39 dB compared to the previous work in [9].

• Journal of Korea Multimedia Society
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• v.18 no.6
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• pp.723-733
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• 2015

High availability is of utmost importance in real-time embedded systems. Temporary failures due to software or hardware faults should not result in a system crash. To achieve high availability, embedded systems typically use a combination of hardware and software techniques. A watchdog timer is a hardware component in embedded microprocessors that can be used to automatically reset the processor if software anomalies are detected. The embedded system relies on a single watchdog timer, however, can be permanently disabled if the timer is not properly configured, e.g. falling into an indefinite loop. STM32F4 provides two different types of watchdog timer in terms of timing accuracy and robustness. In this paper, we propose a hybrid approach, called long-tail watchdog timer, to utilize both timers to achieve self-reliance in embedded systems even though one of timers fails. Experimental results confirm that the proposed approach successfully handles various failure scenarios and present performance comparisons between single watchdog timer and hybrid approach in terms of configuration parameters of watchdog timers in STM32F4, counter value and window size.

• Journal of Korea Multimedia Society
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• v.10 no.8
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• pp.958-966
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• 2007

In this paper, we implement a sound-enhanced MPEG-1 audio decoder on embedded OS Platform. Low bit rate lossy audio codecs such as MP3, OGG, and AAC for mitigating the problems in storage space and network bandwidth suffer a major common problem such as a loss of high frequency fidelity of audio signal. This high frequency loss will reproduce only a band-limited low-frequency part of audio in the standard CD-quality audio. In order to overcome this problem, we embedded a sound enhancement algorithm into the MPEG-1 audio decoder and then the algorithms optimized according to the characteristic of the MPEG-1 audio layer I, II, III were implemented on an embedded OS platform. From the experimental results with spectrum analysis and listening test, we confirm the superiority of the proposed system compared to the standard MPEG-1 audio decoder.

• Journal of Korea Multimedia Society
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• v.11 no.5
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• pp.651-660
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• 2008

Flash memory is widely used in embedded systems because of its benefits such as non-volatile, shock resistant, and low power consumption. However, NAND flash memory suffers from out-place-update, limited erase cycles, and page based read/write operations. To solve these problems, YAFFS and RFFS, the flash memory file systems, are proposed. However YAFFS takes long time to mount the file system, because all the files are scattered all around flash memory. Thus YAFFS needs to fully scan the flash memory. To provide fast mounting, RFFS has been proposed. It stores all the block information, the addresses of block information and meta data to use them at mounting time. However additional operations for the meta data management are decreasing the performance of the system. This paper presents a new NAND flash file system called ERFFS (Efficient and Reliable Flash File System) which provides fast mounting and recovery with minimum mata data management. Based on the experimental results, ERFFS reduces the flash mount/recovery time and the file system overhead.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.368-377
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• 2011

This paper explains the hardware structure of SURF(Speeded Up Robust Feature) based feature point extractor and its FPGA verification result. SURF algorithm produces novel scale- and rotation-invariant feature point and descriptor which can be used for object recognition, creation of panorama image, 3D Image restoration. But the feature point extraction processing takes approximately 7,200msec for VGA-resolution in embedded environment using ARM11(667Mhz) processor and 128Mbytes DDR memory, hence its real-time operation is not guaranteed. We analyzed integral image memory access pattern which is a key component of SURF algorithm to reduce memory access and memory usage to operate in c real-time. We assure feature extraction that using a Vertex-5 FPGA gives 60frame/sec of VGA image at 100Mhz.

• Journal of Korea Multimedia Society
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• v.11 no.10
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• pp.1436-1445
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• 2008

Currently, mobile handset embeds many communication modules including CDMA and Bluetooth, and many applications are developed based on these modules. In this paper, we study about wireless vehicle diagnosis software and user interface based on bluetooth system on mobile handset. We developed Bluetooth communication system on protocol converter between OBD(On Board Diagnostics)-II system. Based on this system, we can communicate ECU(Engine Control Unit) and mobile device based on windows .NET compact framework platform. Therefore we can easily diagnose vehicle state and obtain engine data. All user interface and vehicle diagnosis systems on mobile handset are developed under windows .NET compact framework platform. Using this system we achieved several improvements over existing vehicle diagnostic system; 1) the software download and upgrade can be achieve on wireless environment, 2) no additional diagnostic devices are requires, which saves additional cost and we can diagnose the vehicle easily, 3) we can easily port our system on many embedded systems including PDA and navigator, etc.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.1076-1087
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• 2010

Together with a new advent of embedded processor developed to support specific application area and it evolution, a new research of software development to support the embedded processor and its commercial challenge has been revitalized. Retargetability is typically achieved by providing target machine information, ADL, as input. The ADLs are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, assembler, profiler, and debugger. The EXPRESSION ADL follows a mixed level approach-it can capture both the structure and behavior supporting a natural specification of the programmable architectures consisting of processor cores, coprocessors, and memories. And it was originally designed to capture processor/memory architectures and generate software toolkit to enable compiler-in-the-loop exploration of SoC architecture. In this paper, we designed the class-based ADL based on the EXPRESSION ADL to promote the write-ability, extensibility and verified the validation of grammar. For this works, we defined 6 core classes and generated the EXPRESSION's compiler and simulator through the MIPS R4000 description.

• Journal of Korea Multimedia Society
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• v.10 no.3
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• pp.411-419
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• 2007

Mounted on mobile device, set-top box, or digital TV, EVM is a virtual machine solution that can download and execute dynamic application programs. And the SIL(Standard Intermediate Language) is intermediate language of the EVM, which has a set of opcodes for object-oriented language and a sequential language. Since the C compiler used on each platform depends on the hardware, it converts C program to objective code, and then executes. To solve this problem, our research team developed ANSI C compiler and the EVM. Our ANSI C compiler outputs the SIL code based on stack machine. This paper presents the SIL-to-C decompiler in which converts the SIL code to three address code. Thus, the decompiler allows us to verify SIL code created by ANSI C compiler, and analyze a program from C language source level.

• Journal of Korea Multimedia Society
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• v.19 no.7
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• pp.1179-1187
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• 2016

Through the rapid development of latest hardware technology, high performance as well as miniaturized size is the essentials of embedded system to meet various requirements from the society. It raises possibilities of genuine realization of IoT environment whose size and battery must be considered. However, the limitation of battery persistency and capacity restricts the long battery life time for guaranteeing real-time system. To maximize battery life time, low power technology which lowers the power consumption should be highly required. Previous researches mostly highlighted improving one single type of memory to increase ones efficiency. In this paper, reversely, considering multiple memories to optimize whole memory system is the following step for the efficient low power embedded system. Regarding to that fact, this paper suggests the study of volatile memory, whose capacity is relatively smaller but much low-powered, and non-volatile memory, which do not consume any standby power to keep data, to maximize the efficiency of the system. By executing function in specific memories, non-volatile and volatile memory, the quantitative analysis of power consumption is progressed. In spite of the opportunity cost of all of theses extra works to locate function in volatile memory, higher efficiencies of both power and energy are clearly identified compared to operating single non-volatile memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.82-92
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• 2008

Recently, many digital signal processing(DSP) applications such as H.264, CDMA and MP3 are predominant tasks for modern high-performance portable devices. These applications are generally computation-intensive, and therefore, require quite complicated accelerator units to improve performance. Designing such specialized, yet fixed DSP accelerators takes lots of effort. Therefore, DSPs with multiple accelerators often have a very poor time-to-market and an unacceptable area overhead. To avoid such long time-to-market and high-area overhead, dynamically reconfigurable DSP architectures have attracted a lot of attention lately. Dynamically reconfigurable DSPs typically employ a multi-functional DSP accelerator which executes similar, yet different multiple kinds of computations for DSP applications. With this type of dynamically reconfigurable DSP accelerators, the time to market reduces significantly. However, integrating multiple functionalities into a single IP often results in excessive control and area overhead. Therefore, delay and power consumption often turn out to be quite excessive. In this thesis, to reduce power consumption of dynamically reconfigurable IPs, we propose a novel fine-grained clock gating scheme, and to reduce size of dynamically reconfigurable IPs, we propose a compact multiplier-less multiplication unit where shifters and adders carry out constant multiplications.