• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.51-57
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• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7A
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• pp.814-827
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• 2004

The compressed mode is used to perform inter-frequency and inter-system handover in WCDMA. The instantaneous transmit power is increased in the compressed frame in order to keep the QoS(Quality of Service) unaffected by the reduced processing gain. Furthermore, since the inner loop power control is not active during the transmission gap and the effect of interleaving is decreased, a higher Eb/No target is required, which directly affects the system performance. Due to the impact on performance, the compressed mode should be activated by the RNC(Radio Network Controller) only when there is real need to execute an inter-frequency or inter-system handover. However, 3GPP does not define the method that decides the compressed mode activation. In order to reduce performance degradation, there is need the decision method. In this paper, we consider a combined cell structure in which some neighbor cells have a frequency the same as serving cell and the others have a different frequency or system. Under consideration, we analyze the effect of the compressed mode on the WCDMA forward link performance. In order to avoid performance degradation, we propose an UE(User Equipment) measurement method that can restrict the activation area of the compressed mode of UE that does not need it and evaluate its performance by simulations. Analytical results show that the use of the compressed mode affects the performance degradation. And simulation results show that proposed method leads to better performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.