• Title/Summary/Keyword: 이진코드

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Structural Analysis of Vertical Rope Brake by Spring Type (수직형 스프링식 로프 브레이크의 구조해석)

  • Lee, Jong-Sun;Lee, Jin-Sung;Jung, Myung-Hwa
    • Proceedings of the KAIS Fall Conference
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    • 2006.11a
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    • pp.83-86
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    • 2006
  • 본 논문에서는 수직형 스프링식 로프 브레이크에 관한 것으로 3차원 유한요소해석 코드인 ANSYS를 활용한 구조해석 결과를 기초 데이터로 사용하였으며, 내부응력, 경계조건, 하중등이 고려되었다. 또한 24인승 엘리베이터에 장착되는 로프 브레이크를 대상으로 해석하였다.

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Extracting Symbol Informations from PDF4172-Dimensional Barcode Image (PDF417 이차원 바코드 명상에서 심볼 정보를 추출하는 알고리즘의 구현)

  • 한희일;정정구
    • Proceedings of the Korea Inteligent Information System Society Conference
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    • 2001.06a
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    • pp.347-350
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    • 2001
  • 종래에 사용되어 왔던 1 차원 바코드가 정보를 포함하고 있는 데이터베이스에 접근하는 데이터 키 역할을 주로 해온 것에 비해, 2 차원 바코드는 다량의 데이터를 포함할 수 있고 고밀도의 데이터 표현이 가능하여, 호스트 컴퓨터의 데이터 베이스에 온라인 연결할 필요 없이 확인하고자 하는 사람이나 대상물에 대한 정보를 얻을 수 있다. 본 논문에서는 가장 널리 사용되는 2 차원 바코드 체계인 PDF417 을 중심으로, 디지털 카메라를 통하며 입력한 영상을 이진화하여 시작 심볼 또는 정지 심볼을 검색함으로써 2 차원 바코드 영역을 추출한 다음, 추출된 영역으로부터 바코드의 행과 열의 수, 오류수정 정도 등의 헤더정보를 검출하고 이를 바탕으로 코드정보를 추출하는 알고리즘을 제안한다.

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Recognition of Car License Plates Using Difference Operator and ART2 Algorithm (차 연산과 ART2 알고리즘을 이용한 차량 번호판 통합 인식)

  • Kim, Kwang-Baek;Kim, Seong-Hoon;Woo, Young-Woon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.11
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    • pp.2277-2282
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    • 2009
  • In this paper, we proposed a new recognition method can be used in application systems using morphological features, difference operators and ART2 algorithm. At first, edges are extracted from an acquired car image by a camera using difference operators and the image of extracted edges is binarized by a block binarization method. In order to extract license plate area, noise areas are eliminated by applying morphological features of new and existing types of license plate to the 8-directional edge tracking algorithm in the binarized image. After the extraction of license plate area, mean binarization and mini-max binarization methods are applied to the extracted license plate area in order to eliminated noises by morphological features of individual elements in the license plate area, and then each character is extracted and combined by Labeling algorithm. The extracted and combined characters(letter and number symbols) are recognized after the learning by ART2 algorithm. In order to evaluate the extraction and recognition performances of the proposed method, 200 vehicle license plate images (100 for green type and 100 for white type) are used for experiment, and the experimental results show the proposed method is effective.

A Car License Plate Recognition Using Morphological Characteristic, Difference Operator and ART2 Algorithm (형태학적 특징 및 차 연산과 ART2 알고리즘을 이용한 차량 번호판 인식)

  • Kang, Moo-Jin;Kim, Jae-Kun;Kim, Kwang-Baek
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.10a
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    • pp.431-435
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    • 2008
  • 2006년 11월 이후 신 차량 번호판 등장 후, 신 차량 번호판과 구 차량 번호판이 혼합되어 있다. 이에 따라 속도위반, 신호위반 단속, 무인 주차관리 시스템, 범죄 및 도주 차량 검거, 고속도로 톨게이트에서 통행료 지불로 인한 교통 체증현상을 해소하기 위한 자동 요금 징수와 같은 다양한 경우에서 자동차 번호판의 특징에 맞는 인식 시스템이 요구되고 있다. 따라서 본 논문에서는 이러한 문제를 해결하기 위해 형태학적 특징 및 차 연산과 ART2 알고리즘을 이용한 차량 번호판 인식 방법을 제안한다. 무인 카메라에서 획득된 차량 번호판 영상에서 차 연산을 이용하여 에지를 추출한 후에 블록 이진화를 한다. 이진화 된 차량 영상에서 신 구 차량 번호판의 형태학적 특성을 8방향 윤곽선 추적 알고리즘에 적용하여 잡음 영역을 제거하고, 차량의 번호판 영역을 추출한다 추출된 번호판 영역에 대하여 평균 이진화와 최대 최소 이진화를 적용하여 번호판의 개별 영역에 대한 형태학적 특성을 고려하여 잡음을 제거하고, Labeling 알고리즘을 적용하여 개별 문자를 추출한 후에 결합한다. 이렇게 분류된 개별 문자 및 숫자 코드를 ART2 알고리즘에 적용하여 학습 및 인식을 한다. 제안된 차량 번호판 추출 및 인식 방법의 성능을 평가하기 위해 녹색 번호판과 흰색 번호판 이미지 각각 100장을 대상으로 실험한 결과, 제시 된 차량 번호판 추출 및 인식 방법이 실험을 통해서 효율적인 것을 확인하였다.

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Hardware Implementation of RUNCODE Encoder for JBIG2 Symbol ID Encoding (JBIG2 심벌 ID 부호화를 위한 런코드 부호기의 하드웨어 구현)

  • Seo, Seok-Yong;Ko, Hyung-Hwa
    • Journal of Advanced Navigation Technology
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    • v.15 no.2
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    • pp.298-306
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    • 2011
  • In this paper, the RUNCODE encoder hardware IP was designed and implemented for symbol ID code length encoding, which is one of major modules of JBIG2 encoder for FAX. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the hardware generation and synthesis of VHDL code. The synthesized hardware was downloaded to Virtex-4 FX60 FPGA on ML410 development board. The synthesized hardware utilizes 13% of total slice of FPGA. Using Active-HDL tool, the hardware was verified showing normal operation. Compared with the software operating using Microblaze cpu on ML410 board, the synthesized hardware was better in operation time. The improvement ratio of operation time between the synthesized hardware and software showed about 40 times faster than software only operation. The synthesized H/W and S/W module cooperated to succeed in compressing the CCITT standard document.

A Still Image Compression System with a High Quality Text Compression Capability (고 품질 텍스트 압축 기능을 지원하는 정지영상 압축 시스템)

  • Lee, Je-Myung;Lee, Ho-Suk
    • Journal of KIISE:Software and Applications
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    • v.34 no.3
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    • pp.275-302
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    • 2007
  • We propose a novel still image compression system which supports a high quality text compression function. The system segments the text from the image and compresses the text with a high quality. The system shows 48:1 high compression ratio using context-based adaptive binary arithmetic coding. The arithmetic coding performs the high compression by the codeblocks in the bitplane. The input of the system consists of a segmentation mode and a ROI(Region Of Interest) mode. In segmentation mode, the input image is segmented into a foreground consisting of text and a background consisting of the remaining region. In ROI mode, the input image is represented by the region of interest window. The high quality text compression function with a high compression ratio shows that the proposed system can be comparable with the JPEG2000 products. This system also uses gray coding to improve the compression ratio.

A Study on Minimum Separation Distance for Aboveground High-pressure Natural Gas Pipelines (지상 고압 천연가스 배관의 최소 이격거리 기준에 관한 연구)

  • Lee, Jin-Han;Jo, Young-Do
    • Korean Chemical Engineering Research
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    • v.57 no.2
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    • pp.225-231
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    • 2019
  • In Korea, the minimum separation distance between aboveground high-pressure natural gas pipeline and buildings is regulated by Korea gas safety (KGS) code. In this paper, The technical backgrounds for the revision of the KGS code related to the minimum separation distance was presented. A consequence-based approach was adopted to determine the minimum separation distance by a reasonable accident scenario, which was a jet fire caused by the rupture of one inch branch line attached the gas pipeline. Where, the higher thermal radiation flux threshold was selected for workers in industrial area than for people in non-industrial area, because the workers in industrial area were able to escape in a shorter time than the people in public. As result of consequence analysis for the accident scenario, we suggested the KGS code revision that the minimum separation distances between high-pressure natural gas pipeline installed above ground and buildings should be 30 meter in non-industrial area and 15 meter in industrial area. The revised code was accepted by the committee of the KGS code and now in effect.

The study on Lightness and Performance Improvement of Universal Code (BL-beta code) for Real-time Compressed Data Transferring in IoT Device (IoT 장비에 있어서 실시간 데이터 압축 전송을 위한 BL-beta 유니버설 코드의 경량화, 고속화 연구)

  • Jung-Hoon, Kim
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.15 no.6
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    • pp.492-505
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    • 2022
  • This study is a study on the results of improving the logic to effectively transmit and decode compressed data in real time by improving the encoding and decoding performance of BL-beta codes that can be used for lossless real-time transmission of IoT sensing data. The encoding process of BL-beta code includes log function, exponential function, division and square root operation, etc., which have relatively high computational burden. To improve them, using bit operation, binary number pattern analysis, and initial value setting of Newton-Raphson method using bit pattern, a new regularity that can quickly encode and decode data into BL-beta code was discovered, and by applying this, the encoding speed of the algorithm was improved by an average of 24.8% and the decoding speed by an average of 5.3% compared to previous study.

Light-weight Classification Model for Android Malware through the Dimensional Reduction of API Call Sequence using PCA

  • Jeon, Dong-Ha;Lee, Soo-Jin
    • Journal of the Korea Society of Computer and Information
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    • v.27 no.11
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    • pp.123-130
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    • 2022
  • Recently, studies on the detection and classification of Android malware based on API Call sequence have been actively carried out. However, API Call sequence based malware classification has serious limitations such as excessive time and resource consumption in terms of malware analysis and learning model construction due to the vast amount of data and high-dimensional characteristic of features. In this study, we analyzed various classification models such as LightGBM, Random Forest, and k-Nearest Neighbors after significantly reducing the dimension of features using PCA(Principal Component Analysis) for CICAndMal2020 dataset containing vast API Call information. The experimental result shows that PCA significantly reduces the dimension of features while maintaining the characteristics of the original data and achieves efficient malware classification performance. Both binary classification and multi-class classification achieve higher levels of accuracy than previous studies, even if the data characteristics were reduced to less than 1% of the total size.

Design of 8bit current steering DAC for stimulating neuron signal (뉴런 신호 자극을 위한 8비트 전류 구동형 DAC)

  • Park, J.H.;Shi, D.;Yoon, K.S.
    • Journal of rehabilitation welfare engineering & assistive technology
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    • v.7 no.2
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    • pp.13-18
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    • 2013
  • In this paper design a 8 bit Current Steering D/A Converter for stimulating neuron signal. Proposed circuit in paper shows the conversion rate of 10KS/s and the power supply of 3.3V with 0.35um Magna chip CMOS process using full custom layout design. It employes segmented structure which consists of 3bit thermometer decoders and 5bit binary decoder for decreasing glitch noise and increasing resolution. So glitch energy is down by $10nV{\bullet}sec$ rather than binary weighted type DAC. And it makes use of low power current stimulator because of low LSB current. And it can make biphasic signal by connecting with Micro Controller Unit which controls period and amplitude of signal. As result of measurement INL is +0.56/-0.38 LSB and DNL is +0.3/-0.4 LSB. It shows great linearity. Power dissipation is 6mW.

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