• Journal of the Korea Society of Computer and Information
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• v.15 no.10
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• pp.1-9
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• 2010

In this paper, we propose a methodology in which a power-delay product of a binary adder is optimized based on the heterogeneous adder architecture. We formulate the power-delay product of the heterogeneous adder by using integer linear programming(ILP). For the use of ILP optimization, we adopt a transformation technique in which the initial non-linear expression for the power-delay product is converted into linear expression. The experimental result shows the superiority of the suggested method compared to the cases in which only conventional adder is used.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of Biomedical Engineering Research
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• v.20 no.1
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• pp.107-113
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• 1999

The purpose of this study was to develop a miniature imaging gamma probe with high performance that can detect small or residual tumors after surgery. Gamma probe detector system consists of NaI(Tl) scintillator, position sensitive photomultiplier tube (PSPMT), and collimator. PSPMT was optically coupled with 6.5 mm thick, 7.62 cm diameter of NaI(Tl) crystal and supplied with -1000V for high voltage. Parallel hexagonal hole collimator was manufactured for characteristics of 40-mm hole length, 1.3-mm hole diameter, and 0.22 mm septal thickness. Electronics consist of position and trigger signal readout systems. Position signals were obtained with summing, subtracting, and dividing circuit using preamplifer and amplifier. Trigger signals were obtained using summing amplifier, constant fraction discriminator, and gate and delay generator module with preamplifer. Data acquisition and processing were performed by Gamma-PF interface board inserted into pentium PC and PIP software. For imaging studies, flood and slit mask images were acquired using a point source. Two hole phantom images were also acquired with collimator. Intrinsic and system spatial resolutions were measured as 3.97 mm and 5.97 mm, respectively. In conclusion, Miniature gamma probe images based on the PSPMT showed good image quality, we conclude that the miniature imaging gamma probe was successfully developed and good image data were obtained. However, further studies will be required to optimize imaging characteristics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.3
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• pp.517-524
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• 2001

This paper describes a design of radix-2 SRT divider unit, which supports IEEE-754 floating-point standard, using redundant binary number system (RBNS). With the RBNS, the partial quotient decision logic can operate about 20-% faster, as well as can be implemented with a simple hardware when compared to the conventional methods based on two's complement arithmetic. By using a new redundant binary adder proposed in this paper, the mantissa divider is efficiently implemented, thus resulting in about 20% smaller area than other works. The divider unit supports double precision format, five exceptions and four rounding modes. It was verified with Verilog HDL and Verilog-XL.