• Journal of KIISE:Computer Systems and Theory
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• v.36 no.2
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• pp.102-110
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• 2009

The memory wall is the growing disparity of speed between CPU and memory outside the CPU chip. An economical solution is a memory hierarchy organized into several levels, such as processor registers, cache, main memory, disk storage. We introduce a novel memory hierarchy optimization technique in Linux based embedded systems using on-chip SRAM for the first time. The optimization technique allocates On-Chip SRAM to the code/data that selected by programmers by using virtual memory systems. Experiments performed with nine applications indicate that the runtime improvements can be achieved by up to 35%, with an average of 14%, and the energy consumption can be reduced by up to 40%, with an average of 15%.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.10
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• pp.541-547
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• 2001

Testing a core-based designed chip requires a full isolation ring to provide fro core test data access to each core. A partial isolation ring replaces the full isolation ring reducing total isolation ring size surrounding. This paper proposes an efficient method to reduce the size of the partial isolation ring and shorten the time to acquire the final solution. For this, a reasonable ordering technique according to testability is introduced and a sorting technique is adopted to reduce the total solution time. Experimental results show that the proposed method can be useful in practice.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.7_8
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• pp.370-380
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• 2003

A large RAID system may consist of several PCI bus segments since a PCI bus segment can connect only a limited number of disks. In this paver, PCI bus transactions in a RAID system are classified in terms of the initiator and the target of the transaction. Also, the data transfer time of each transaction type is analyzed. By using the analysis results, read and write performance of two RAID system configurations are formulated. From simulation of the RAID system using the DEVS formalism, performance of the configurations are evaluated and compared with the analytical results while changing various system parameters.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.1
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• pp.82-97
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• 1999

3차원 그래픽 렌더링은 화면상의 각 화소에 대하여 색깔뿐만 아니라 깊이 정보가지 계산해야 하기 때문에 방대한 계산량과 메모리 접근, 그리고 데이터 전송량을 필요로 하기 때문이다. 따라서 실시간 3차원 그래픽 처리를 위해서 병렬 처리 기법을 도입한다. 그러나 기존 그래픽 가속엔진은 병렬처리 기법으로 영상-병렬성을 이용한 화면 분할 방식을 사용하기 때문에 크게 두 가지 단점이 발생한다. 첫 번재는 화면 영역의 경게에 위치하는 다각형들에 대한 중복계산이고, 두 번째는 낮은 PE(Processing Element) 활용도이다. 본 논문에서는 이러한 문제를 해결하기 위한 방법으로 객체 기반 렌더링(OBR : Object Based Rendering)방식을 바탕으로 하는 그래픽 가속엔진을 제안하였다. OBR 시스템의 목적은 화면 분할 방식의 불필요한 오버헤드를 제거하여 수행 성능을 높이고, 자원을 효율적으로 사용하여 하드웨어 구성비용을 줄이는 것이다. 본 논문에서는 시뮬레이션을 통하여 OBR 시스템이 화면 분할 방식의 대표적인 그래픽 가속기인 PixelFlow와의 성능을 상대적으로 비교하였다. 결론적으로 OBR 시스템은 화면 분할 방식보다 더 적은 하드웨어 자원으로 보다 효율적으로 렌더링을 수해하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.253-259
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• 2019

The wedding seating problem(WSP) is to finding a minimum loss of guest relations(sit together preference) with restricted seats of a table for complex guest relation network. The WSP is NP-hard because of the algorithm that can be find the optimal solution within polynomial-time is unknown yet. Therefore we can't solve the WSP not computer-assisted programming but by hand. This paper suggests min-cut rule theory that the two guests with maximum preference can't separate in other two tables because this is not obtains minimum loss of preference. As a result of various experimental, this algorithm obtains proper seating chart meet to the seats of a table constraints.

• Journal of KIISE:Information Networking
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• v.28 no.3
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• pp.389-405
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• 2001

In these days, we have increasing demands on the real-time services, especially for the multimedia data transmission in both of wired and wireless environments and thus efficient and stable ways of transmitting realtime data are needs. Although RTP is widely used for internet-based realtime applications, it cannot avoid packet losses, due to the use of UDP stack and its underlying layers. In the case of mobile computing applications, the packet losses are more frequent and consecutive because of the limited bandwidth. In this paper, we first statistically analyze the characteristics of packet losses in the wired and wireless communications, based on Gilbert model, and a new packet recovery scheme for realtime data transmission is presented. To reflect the transmission characteristics of the present network environment, our scheme makes the sender to dynamically adjust the amount of redundant information, using the current packet loss characteristic parameters reported by the receiver. Additionally, we use relatively large and discontinuous offset values, which enables us to recover from both of the random and consecutive packet losses. Due to these characteristics, our scheme is suitable for the mobile computing environment where packet loss rates are relatively high and varies rapidly in a wide range. Since our scheme is based on the analytic model form statistics, it can also be used for other network environments. We have implemented the scheme with Mobile IP and RTP/RTCP protocols to experimentally verify its efficiency.

• Journal of KIISE:Software and Applications
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• v.36 no.8
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• pp.607-615
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• 2009

There has recently been a trend that IT industry is united with traditional industries such as military, aviation, automobile, and medical industry. Therefore, embedded software which controls hardware of the system should guarantee the high reliability, availability, and maintainability. To guarantee these properties, there are many attempts to develop the embedded software based on COTS (Commercial Off The Shelf) hardware components. However, it can cause additional faults due to software/hardware interactions beside general software faults in this methodology. We called the faults, Linkage Fault. These faults have high severity that makes overall system shutdown although their occurrence frequency is extremely low. In this paper, we propose a new software reliability model which considers those linkage faults in embedded software development with COTS hardware components. We use the Bayesian Analysis and Markov Chain Monte-Cairo method to validate the model. In addition, we analyze real linkage fault data to support the results of the theoretical model.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.2
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• pp.90-102
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• 2010

Flash memory has been widely used as an important storage device for consumer electronics. For the flash memory-based storage systems, FTL (Flash Translation Layer) is used to handle the mapping between a logical page address and a physical page address. Especially, log buffer-based FTLs provide a good performance with small-sized mapping information. In designing the log buffer-based FTL, one important factor is to determine the mapping structure between data blocks and log blocks, called associativity. While previous works use static associativity fixed at the design time, we propose a new log block mapping scheme which adjusts associativity based on the run-time workload. Our proposed scheme improves the I/O performance about 5~16% compared to the static scheme by adjusting the associativity to provide the best performance.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.3
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• pp.199-209
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• 2009

In this paper, we suggest a stroke level of detail (LOD) based on a saliency density. On painter]y rendering, the stroke LOD has an advantage of making the observer concentrate on the main object and improving accuracy of expression. For the stroke LOD, it is necessary to classify the detailed and abstracted area. We divide the area on the basis of saliency distribution and the level of detailed expression is controlled based on the saliency information. 'We define that the area of which the saliency distribution is high is a major subject that an artist tries to express, it is described in detail. The area of which the saliency distribution is low is abstractly described. Each divided area has the abstraction level. And by adapting the brushes of which sizes are appropriate to each level, it is possible to express the area which needs to be expressed in details from the one which needs to be expressed abstractly.

• KIISE Transactions on Computing Practices
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• v.21 no.9
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• pp.596-603
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• 2015

A concept network is an essential knowledge base for semantic search engines, personalized search systems, recommendation systems, and text mining. Recently, studies of extending concept representation using external ontology have been frequently conducted. We thus propose a new way of building 3-dimensional text model-based concept networks using the world knowledge-level Wikipedia ontology. In fact, it is desirable that 'concepts' derived from text documents are defined according to the theoretical framework of formal concept analysis, since relationships among concepts generally change over time. In this paper, concept networks hidden in a given document collection are extracted more reasonably by representing a concept as a term-by-document matrix.