• Title/Summary/Keyword: 이득조절

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Feasibility of hearing aid gain self-adjustment using speech recognition (말소리 인지를 이용한 보청기 이득 자가 조절의 실현)

  • Yun, Donghyeon;Shen, Yi;Zhang, Zhuohuang
    • The Journal of the Acoustical Society of Korea
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    • v.41 no.1
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    • pp.76-86
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    • 2022
  • Personal hearing devices, such as hearing aids, may be fine-tuned by allowing the users to conduct self-adjustment. Two self-adjustment procedures were developed to collect the listener preferred gains in six octave-frequency bands from 0.25 kHz to 8 kHz. These procedures were designed to allow rapid exploration of a multi-dimensional parameter space using a simple, one-dimensional user control interface (i.e., a programmable knob). The two procedures differ in whether the user interface controls the gains in all frequency bands simultaneously (Procedure A) or only the gain in one frequency band (Procedure B) on a given trial. Monte-Carlo simulations suggested that for both procedures the gain preference identified by simulated listeners rapidly converged to the ground-truth preferred gain profile over the first 20 trials. Initial behavioral evaluations of the self-adjustment procedures, in terms of test-retest reliability, were conducted using 20 young, normal-hearing listeners. Each estimate of the preferred gain profile took less than 20 minutes. The deviation between two separate estimates of the preferred gain profile, conducted at least a week apart, was about 10 dB ~ 15 dB.

Automatic Gain Control Algorithms for MB-OFDM UWB System (MB-OFDM UWB에서 효율적인 자동 이득 조절 장치)

  • Hong, Dae-Ki
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.8 no.6
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    • pp.1402-1409
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    • 2007
  • In this paper, we propose various types of AGC algorithms for implementing the OFDM communication systems. For the high-speed packet transmission, in this paper, we assume the OFDM system with relatively long and repeated preambles. We propose the maximum sample value counter for counting the number of maximum sample. In the maximum sample value counter, we use the buffer for the digital signal buffering. Finally, the counting value of the maximum sample value counter controls the gain control signal generator by using gain control table automatically.

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A New Variable Degeneration Resistor for Digitally Programmable CMOS VGA (디지털 방식의 이득조절 기능을 갖는 CMOS VGA를 위한 새로운 가변 축퇴 저항)

  • Kwon, Duck-Ki;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.7 no.1 s.12
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    • pp.43-55
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    • 2003
  • A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome the problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. The proposed gain control scheme makes it easy to implement a low-voltage and high-speed VGA. This paper describes the problems existed in conventional methods, the principle and advantages of the proposed scheme, and their performance comparison in detail. A CMOS VGA cell is designed using the proposed degeneration resistor. The 3dB bandwidths are greater than 650㎒ and the gain errors are less than 0.3dB in a gain control range from -12dB to +12dB in 6dB steps. It consumes 3.1㎃ from a 2.5V supply voltage.

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Design of Ku-band Channel Amplifier Engineering Model for Communication and Broadcasting Satellite Payload (통신방송위성 중계기용 Ku-대역 채널증폭기 시험 모델 설계)

  • 장병준;염인복;이성팔
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.10
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    • pp.982-988
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    • 2002
  • This paper summarizes the design concepts and implementation of a Ku-band channel amplifier's engineering model for the communication and broadcasting satellite applications. The selected architecture uses the analog gain control for the FGM(Fixed Gain Mode) and the output level limiting using automatic loop control for the ALC (automatic level control) mode. The Ku-band channel amplifier incorporates several state-of-the-art components including voltage-controlled PIN diode attenuators, and various temperature-compensation circuits. The measured characteristics of the Ku-band channel amplifier are in good agreement with the expected performance. The results show a fixed gain control of 28 dB, and an automatic level control of 16 dB over operating temperature range. The designed engineering model could be used as a channel amplifier for Ku-band communication and broadcasting satellite payload system.

60dB 0.18μm CMOS Low-Power Programmable Gain Amplifier (60dB 0.18μm CMOS 저전력 이득 조절 증폭기)

  • Park, Seung-Hun;Lee, Jung-Hoon;Kim, Cheol-Hwan;Ryu, Jee-Youl
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.05a
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    • pp.349-351
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    • 2013
  • This research paper presents a low-power programmable gain amplifier (PGA) to facilitate signal processing of the detection of defects in steel plates. This circuit is able to adjust a gain in the range of 6 to 60dB in 7 steps using different signal types for various defects from hall sensors. The gain of PGA is designed by operating on-resistors of switches and passive components. The proposed PGA ($0.18{\mu}m$ CMOS process with 1.8 supply voltage) showed excellent gain error of less than -0.2dB, and low power consumption of 0.47mW.

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Design & Fabrication of a Broadband SiGe HBT Variable Gain Amplifier using a Feedforward Configuration (Feedforward 구조를 이용한 광대역 SiGe HBT 가변 이득 증폭키의 설계 및 제작)

  • Chae, Kyu-Sung;Kim, Chang-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.5A
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    • pp.497-502
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    • 2007
  • Broadband monolithic SiGe HBT variable gain amplifier with a feedforward configuration have been newly developed to improve bandwidth and dB-linearly controlled gain characteristics. The VGA has been implemented in a $0.35-{\mu}m$ BiCMOS process. The VGA achieves a dynamic gain-control range of 19.6 dB and a 3-dB bandwidth of 4 GHz ($4{\sim}8\;GHz$) with the control-voltage range from 0.6 to 2.6 V. The VGA produces a maximum gain of 9.3 dB at 6 GHz and a output power of -3 dBm at 8 GHz.

Design of a Programmable Gain Amplifier with Digital Gain Control Scheme using CMOS Switch (CMOS 스위치를 이용한 디지털 이득 제어 구조의 PGA 설계)

  • Kim, Cheol-Hwan;Park, Seung-Hun;Lee, Jung-Hoon;Lim, Jae-Hwan;Lee, Joo-Seob;Choi, Geun-Ho;Lim, Yoon-Sung;Ryu, Jee-Youl
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.354-356
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    • 2013
  • 본 논문에서는 CMOS 스위치를 이용한 디지털 이득 제어 구조를 가진 이득 조절 증폭기 (PGA, Programmable Gain Amplifier)를 제안한다. 기존의 아날로그 이득 제어 방식에서는 가변적인 트랜스 컨덕턴스를 활용하는 과정에서 바이어스 전류나 전압에 의해 이득이 변하게 되어 순간적으로 구성회로의 바이어스 포인트가 변하기 때문에 왜곡이 발생하게 되는 문제점이 있다. 본 논문에서는 이러한 문제점을 해결하기 위해 기존의 gm-boosting 증폭기를 변형한 디지털 이득 제어 방식으로 설계되어 있기 때문에 우수한 선형성을 가지며 특수 목적에 맞도록 그 이득을 6dB에서 60dB까지 7가지 단계로 조절 가능하다. 제안한 PGA는 기존 회로에 비해 0.2dB 보다 작은 이득오차와 0.47mW의 낮은 소비전력 특성을 보였다.

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A study on the Speed Control of SPMSM Using the Variable Gain (가변 Gain을 이용한 SPMSM의 속도제어에 관한 연구)

  • Lee J.H.;Jo U.K.;Kim C.U.
    • Proceedings of the KIPE Conference
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    • 2004.07a
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    • pp.15-18
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    • 2004
  • 본 논문에서는 표면 부착형 영구자석형 동기 전동기(SPMSM)의 가감속과 부하 변동에 따른 속도 특성 향상을 위해 실제 속도와 부하 토크 관측기를 통한 부하 토크를 입력 변수로 설정하여 가변 이득 조절 알고리즘을 제안한다. 제안된 알고리즘을 증명하기 위해 여러 운전 조건에서 기존의 이득 시스템과 가변 이득 조절 시스템을 비교하여 제안된 알고리즘의 효용성을 검증하였다.

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A Design of Voltage-controlled frequency Tunable Integrator (전압조절 주파수 가변 적분기 설계)

  • 이근호;이종인
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.6
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    • pp.891-896
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    • 2002
  • In this paper, a new voltage-controlled tunable integrator for low-voltage applications is proposed. The proposed active element is composed of the CMOS complementary cascode circuit which can extend transconductance of an element. Therefore, the unity gain frequency which is determined transcon-ductance is increased than that of the conventional element. And then these results are verified by the $0.25{\mu}m$ CMOS n-well parameter HSPICE simulation. As a result, the gain and the unity gain frequency are 42dB and 200MHz respectively in the element on 2V supply voltage. And power dissipation of the designed circuit is 0.32mW.

A design of predistortion linearizer using the feedback (Feedback 방식을 이용한 전치왜곡기 설계)

  • 남윤관;조범식;권성수;강원석;오인열
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2000.11a
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    • pp.202-205
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    • 2000
  • 본 논문에서는 IMT-2000용 고전력 중폭기에 사용할수 있근 전치 왜곡기를 feedback 방식을 이용하여 설계하였다. 여기서 feedback 방식을 사용함으로써 기존의 전치 왜곡기와는 달리 증폭기의 이득을 조절하기 위해 감쇄기를 사용하지 않고 feedback에 사용한 저항값을 사용하여 이득을 조절하도록 설계하였다.

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