• Proceedings of the KAIS Fall Conference
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• 2007.11a
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• pp.297-299
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• 2007

본 논문은 유한한 유전체 격자구조에 입사되는 TE필드가 유전체 내부에 발생시키는 모드의 필드 분포와 방출하는 필드를 분석하였다. 입사되는 필드는 유전체 격자구조에 일정한 패턴의 모드를 형성한다. 유한한 길이의 격자구조의 영향을 받아 유전체 내부에 유한개의 모드가 만들어지며 모드들은 각기 독립적인 방사패턴을 갖는다. 이러한 방사패턴을 분석함으로써 실제로 제작되는 유전체 격자구조의 분석에 도움이 될 것으로 사료된다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.3
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• pp.645-648
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• 2008

In this paper, we analyze inner- and far-field emitted field pattern by more exactly calculating modes formed from a finite periodic dielectric structure(FPDS). It is assumed that TE-modes are generated in FPDS, and the fields in each layer are determined by proper boundary conditions. Consequently, the fields generate modes in the FPDS and the number of modes depends on its structural characteristics. In this work, the modes betwween dielectric layers and their field patterns are calculated in a specific frequency. In addition. far field patterns are given by using FFT of the calculated modes.

• Journal of the Korea Society of Computer and Information
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• v.13 no.2
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• pp.193-201
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• 2008

Using Network Coding in P2P systems yields great benefits, e.g., reduced download delay. The core notion of Network Coding is to allow encoding and decoding at intermediate nodes, which are prohibited in the traditional networking. However, improper implementation of Network Coding may reduce the overall performance of P2P systems. Network Coding cannot work with general arithmetic operations, since its arithmetic is over a Finite Field and the use of an efficient Finite Field arithmetic algorithm is the key to the performance of Network Coding. Also there are other important performance parameters in Network Coding such as Field size. In this paper we study how those factors influence the performance of Network Coding based systems. A set of experiments shows that overall performance of Network Coding can vary 2-5 times by those factors and we argue that when developing a network system using Network Coding those performance parameters must be carefully chosen.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.6
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• pp.289-300
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• 2001

본 논문에서는 유한 필드 GF(2$_{m}$ ) 상에서 모듈러 곱셈 A($\chi$)B($\chi$) mod P($\chi$)을 수행하는 새로운 선형 문제-크기(full-size) 시스톨릭 어레이 구조인 LSB-first 곱셈기를 제안한다. 피연산자 B($\chi$)의 LSB(least significant bit)를 먼저 사용하는 LSB-first 모듈러 곱셈 알고리즘으로부터 새로운 비트별 순환 방정식을 구한다. 데이터의 흐름이 규칙적인 순환 방정식을 공간-시간 변환으로 새로운 시스톨릭 곱셈기를 설계하고 분석한다. 기존의 곱셈기와 비교할 때 제안한 곱셈기의 면적-시간 성능이 각각 10%와 18% 향상됨을 보여준다. 또한 같은 설계방법으로 곱셈과 제곱연산을 동시에 수행하는 새로운 시스톨릭 곱셈/제곱기를 제안한다. 유한 필드상의 지수연산을 위해서 제안한 시스톨릭 곱셈/제곱기를 사용할 때 곱셈기만을 사용 할 때보다 면적-시간 성능이 약 26% 향상됨을 보여준다.

• Proceedings of the KAIS Fall Conference
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• 2008.11a
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• pp.264-266
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• 2008

본 논문은 유한한 유전체 격자구조의 정확한 주파수 선택 특성을 해석하고자 새로운 방법을 제시하였다. 기존의 오차, 근사화를 갖고 있는 해석방법과는 달리 유한한 구조에서 근사화가 전혀 없는 방법을 제시하였다. 유한한 격자구조의 유전체는 내부에 존재하는 필드 분포가 한정되어 있으며 구조 파라메터등에 따라 유한한 모드만이 생길 수 있어 입사되는 필드에 따른 생성 모드가 한정되어 있다. 본 논문은 이러한 방법을 이용하여 유전체 격자구조의 주파수 선택특성에 활용에 이용될 수 있을 것으로 사료된다.

• KOREAN POULTRY JOURNAL
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• v.54 no.4
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• pp.116-120
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• 2022

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.281-286
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• 2002

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.1_2
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• pp.62-68
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• 2006

The important arithmetic operations over finite fields include multiplication and exponentiation. An exponentiation operation can be implemented using a series of squaring and multiplication operations over GF($2^m$) using the binary method. Hence, it is important to develop a fast algorithm and efficient hardware for multiplication. This paper presents an efficient bit-serial systolic array for MSB-first multiplication in GF($2^m$) based on the polynomial representation. As compared to the related multipliers, the proposed systolic multiplier gains advantages in terms of input-pin and area-time complexity. Furthermore, it has regularity, modularity, and unidirectional data flow, and thus is well suited to VLSI implementation.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.190-194
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• 2002

Multiplication in Galois Field GF(2/sup m/) is a primary operation for many applications, particularly for public key cryptography such as Diffie-Hellman key exchange, ElGamal. The current paper presents a new architecture that can process Montgomery multiplication over GF(2/sup m/) in m clock cycles based on cellular automata. It is possible to implement the modular exponentiation, division, inversion /sup 1)/architecture, etc. efficiently based on the Montgomery multiplication proposed in this paper. Since cellular automata architecture is simple, regular, modular and cascadable, it can be utilized efficiently for the implementation of VLSI.