• Korean Journal of Materials Research
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• v.9 no.9
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• pp.861-864
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• 1999

A new plasma source using the multi-cathode electron beam has been designed and manufactured. A multi-cathode was adopted to produce bulk plasmas in a large volume. Multi-cathode electron beam plasma source(MCEBPS) was found to generate stable plasmas over the wafer diameter of 300 mm or above. W(tungsten) filament was used as a cathode. Over a 320 mm diameter, both the plasma potential $V_p$ and floating potential $V_f$ were uniformly maintained and the difference between $V_p and V_f$ was measured to be small. The plasma density was around $10^{10} cm^{-3}$ and its variation along the radial distance was small.

• Journal of Sensor Science and Technology
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• v.8 no.2
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• pp.202-209
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• 1999

Microstrip line was fabricated on the oxidized porous silicon layer which has nearly electrically and chemically identical properties with thermally oxidized silicon layer. Thick oxidized porous silicon layer of few tenth of micrometers was prepared by thermal oxidation of porous silicon layer on silicon substrate. Multi-step thermal oxidation process was used to obtain high Quality and thick oxidized silicon layer and to release thermal stress. Microstrip line was fabricated on the oxidized porous silicon layer. Its microwave characteristics were measured and the availability for MMIC substrate was investigated.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.613-613
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• 2013

그래핀은 저차원계 구조에서 기인하는 뛰어난 전기적, 물리적, 기계적 성질을 지니고 있어 실리콘 기반 기술을 대체할 전계 효과 트랜지스터 이외에도 투명전극, 초고용량 커패시터, 전계방출 디스플레이 등 다양한 응용분야에 적용 가능하다. 최근에는 이러한 응용 연구분야에서 그래핀과 탄소나노튜브 각각의 단점을 최소화하고 장점을 극대화하기 위한 그래핀-탄소나노튜브 혼성 나노구조에 대한 연구들이 진행되고 있는 추세이다. 이전 연구들에서 환원된 그래핀 산화물(Reduced Graphene Oxide, RGO)을 이용한 그래핀-탄소나노튜브 혼성 나노구조가 제작되었는데, 이는 RGO의 제작과정에서 복잡한 공정과 긴 합성과정이 요구될 뿐 아니라, 복합 물질에서 탄소나노튜브의 밀도 제어가 어렵다는 단점을 지닌다. 또한 현재까지 제작된 그래핀-탄소나노튜브 혼성 나노구조의 경우, 열 화학기상증착법으로 합성된 다층(few-layers)의 그래핀과 탄소나노튜브 혼성 나노구조를 제작하였다 [1-6]. 본 연구에서는 우수한 전기적 특성을 가진 단층(monolayer)의 그래핀을 열 화학기상증착법으로 합성한 후, 그래핀 위에 단일벽 탄소나노튜브를 성장시킴으로써 그래핀-탄소나노튜브 혼성 나노구조를 제작하였다. 합성된 그래핀-탄소나노튜브의 구조적 특징은 주사 전자 현미경과 라만 분광기 측정을 통해 확인하였고, 촉매의 표면 형상 및 화학적 상태는 원자힘 현미경과 X선 광전자 분광법을 통해 확인하였다. 또한 그래핀 기반의 전계 효과 트랜지스터의 경우, 상온에서 그래핀은 우수한 전하 이동도를 가지며 웨이퍼 스케일에서 제작하기 쉬우나 밴드 갭이 없으므로 높은 Ion/Ioff를 가지는 그래핀 기반의 트랜지스터를 만드는 것이 과제이다. 반면 탄소나노튜브는 큰 에너지 갭을 가지고 있으므로 높은 Ion/Ioff를 구현하는 소자 제작이 가능하다. 그리하여 제작된 그래핀-탄소나노튜브 혼성 나노구조의 소자 제작을 통해 전기적 특성을 조사하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.383-389
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• 2001

We report on the design, fabrication, and characterization of 0.35${\mu}{\textrm}{m}$-gate AIGaAs/InGaAs PHEMTs for millimeter-wane applications. The epi-wafer structures were designed using ATLAS for optimum DC and AC characteristics, 0.351m-gate AIGaAs/rnGaAs PHEMTs having different gate widths and number of fingers were fabricated using electron beam lithography Dependence of RF characteristics of PHEMT on gate finger with and number of gate fingers have been investigated. PHEMT haying two 0.35$\times$60${\mu}{\textrm}{m}$$^2$ gate fingers showed the knee voltage, pinch-off voltage, drain saturation current density, and maximum transconductance of 1.2V, -1.5V, 275㎃/mm, and 260.17㎳/mm, respectively. The PHEMT showed fT(equation omitted)(current gain cut-off frequency) of 45㎓ and fmax(maximum oscillation frequency) of 100㎓. S$_{21}$ and MAG of the PHEMT were 3.6dB and 11.15dB, respectively, at 35㎓

• Journal of the Korean Ceramic Society
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• v.38 no.12
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• pp.1150-1154
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• 2001

Silicon oxynitride (SiON) thick films using the core layer of silica optical waveguide have been deposited on Si wafer by PECVD at low temperature (32$0^{\circ}C$) were obtained by decomposition of appropriate mixture of (SiH$_4$+$N_2$O+$N_2$) gaseous mixtures under RF power and SiH$_4$/($N_2$O+$N_2$) ratio deposition condition. Prism coupler measurements show that the refractive indices of SiON layers range from 1.4663 to 1.5496. A high SiH$_4$/($N_2$O+$N_2$) of 0.33 and deposition power of 150 W leads to deposition rates of up to 8.67 ${\mu}{\textrm}{m}$/h. With decreasing SiH$_4$/($N_2$O+$N_2$) ratio, the SiON layer become smooth from 41$\AA$ to 6$\AA$.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.3
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• pp.334-338
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• 1999

Porous silicon layers were fabricated with various conditions of HF concentration and current density. And their masses were measured. From these data, the porosity and fractal dimension were estimated and analyzed. We found that the porosity was proportional to the current density when the anodic reaction time was fixed and the constant values of fractal dimension could be estimated from a series of data with fixed HF concentration. The values of fractal dimension were decreased with increasing HF concentration. The obtained porosity and fractal dimension were compared with the 2-dimensional computer simulation based on diffusion limited deposition model. According to the simulation, the porosity was proportional to the diffusion length and the fractal dimension was inversely proportional to the diffusion length. Since, the diffusion length is proportional to current density and inversely proportional to base concentration, our experimental data qualitatively agreed with the results from the simulation. The porosity obtained by experiments, however, was not consistent with the results by simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.661-669
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• 1999

A probe card is one of the most important pan of test systems as testing IC(integrated circuit) chips. This work was related to bump-type silicon vertical probe card which enabled simultaneous tests for multiple semiconductor chips. The probe consists of silicon cantilever with bump tip. In order to obtain optimum size of the cantilever, the dimensions were determined by FEM(finite element method) analysis. The probe was fabricated by RIE(reactive ion etching), isotropic etching, and bulk-micromachining using SDB(silicon direct bonding) wafer. The optimum height of the bump of the probe detemimed by FEM simulation was 30um. The optimum thickness, width, and length of the cantilever were 20 $\mum$, 100 $\mum$,and 400 $\mum$,respectively. Contact resistance of the fabricated probe card measured at contact resistance testing was less than $2\Omega$. It was also confirmed that its life time was more than 20,000 contacts because there was no change of contact resistance after 20,000 contacts.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.11
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• pp.1765-1771
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• 2010

In the case of micro.electro-mechanical system (MEMS) devices, the quality of punched via hole is one of the most important factors governing the performance of the device. The common features that affect the laser micromachining of via holes drilled by using Nd:$YVO_4$ laser are described, and efficient optimization methods to measure them are presented. The analysis methods involving an orthogonal array, analysis of variance (ANOVA), and response surface optimization are employed to determine the main effects and to determine the optimal laser process parameters. The significant laser process parameters were identified and their effects on the quality of via holes were studied. Finally, an experiment in which the optimal levels of the laser process parameters were used was carried out to demonstrate the effectiveness of the optimization method.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.25.1-25.1
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• 2009

Pattern 웨이퍼 상의 오염입자 제거는 반도체 산업의 주된 과제 중 하나이다. Pattern의 선폭이 좁아짐에 따라 Pattern에 손상을 가하지 않고 오염입자를 제거 하는 것은 더욱 어려워지고 있다. 그뿐만 아니라 기존 습식세정 공정에서의 화학액에 의한 환경오염 및 박막의 손실도 문제가 되기 시작했다. 이러한 문제를 해결하기 위해 기존 세정공정에서 화학액의 농도를 낮추고 Megasonic 등을 이용하여 세정력을 보완하는 방법들이 연구되고 있다. 하지만 습식세정의 경우 강한 화학작용으로 인한 표면 손상 및 물 반점의 문제는 여전히 이슈가 되고 있다. 이러한 단점을 극복하기 위하여 건식 세정법이 제시되고 있으며 이 중 레이저 충격파는 레이저를 집속시켜 발생된 충격파를 이용하여 입자를 제거하기 때문에 국부적인 세정이 가능하며 세정력 조절이 가능하여 손상이 세정을 할 수 있다. 그러나 Pattern의 구조에 의해 전되는 세정력의 차이가 발생하고 Trench 내부의 오염입자제거 문제점이 발생할 수 있다. 시편은 Si STI Pattern을 100 nm PSL Particle (Red Fluorescence, Duke Scientific, USA) 을 50ppm 농도로 희석시킨 IPA에 dipping 하여 오염시킨 후 N2 Gas를 이용하여 건조하여 준비하였다. 그리고 레이저 충격파 세정 시스템은 최대 에너지 1.8 J까지 가능한 레이저를 발생하는 1,064 nm Nd:YAG 레이저를 이용하여 실험하였다. 레이져 충격파 실험은 충격파와 시편사이의 거리, gap distance와 에너지를 변환하여 세정효율을 관찰하였다. 세정효율은 세정 전후의 입자 감소량을 현광현미경 (LV-150, Nikon, Japan)를 이용하여 측정하였다. 그 결과, Trench 내부의 오염입자의 경우 Trench 밖의 오염입자에 비해 세정효율이 떨어지는 것으로 나타났으나 시편과 레이저 초점과의 거리가 가까워짐에 따라 Trench 내부의 오염입자에 대한 세정 효율을 증가시킬 수 있었다.

• Korean Journal of Optics and Photonics
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• v.16 no.2
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• pp.113-120
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• 2005

Luminous efficiency and uniformity in a LCD-BLU are mainly determined by fine scattering patterns formed on the light guide panel. We propose a novel fabrication method of 3-dimensional scattered patterns based on anisotropic etching of silicon wafers. Micro-pyramid patterns with 70.5 degree apex-angle and micro-prism patterns with 109.4 degree apex-angle can be self-constructed by the wet, anisotropic etching of (100) and (110) silicon wafers, respectively, and those patterns are easily duplicated by the PDMS replica process. Experimental results on spatial and angular distributions of irradiation from the light guide panel with the micro-pyramid patterns were very consistent with the calculation results. Surface roughness of the silicon-based micro-patterns is free from any artificial defects since the micro-patterns are inherently formed with silicon crystal surfaces. Therefore, we expect that the silicon based micro-patterning process makes it possible to fabricate perfect 3-dimensional micro-structures with crystal surface and apex angles, which may guarantee mass-reproduction of the light guide panels in LCD-BLU.