• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1405-1409
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• 2004

This paper is studied new block mode decision algorithm for H.264/AVC. The fast block mode decision algorithm is consist of block range decision algorithm. The block range decision algorithm classifies the block over 8$\times$8 size or below for 16${\times}$16 macroblock to decide the size and type of sub blocks. As the sub blocks of 8$\times$8, 8r4, 4$\times$8 and 4$\times$4, which are the blocks below 8$\times$8 size, include important motion information, the exact sub block decision is required. RDC(RDO cost) is used as the matching parameter for the exact sub block decision. RDC is calculated with motion strength which is the mean value of neighbor pixels of each sub block. The sub block range decision reduces encoding arithmetic amount by 34.62% on the average more than the case not using block range decision. The block mode decision using motion strength shows improvement of PSNR of 0.05[dB].

• The Journal of the Acoustical Society of Korea
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• v.30 no.5
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• pp.239-248
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• 2011

In order to improve the quality of strain images in medical ultrasound imaging, displacements need to be accurately estimated. In this paper, in order to apply one-dimensional displacement estimation methods to two-dimensional motion estimation, the axial and lateral displacements are separately estimated. In order to estimate lateral displacements, one-dimensional signals aligned in the lateral direction are converted to analytic signals, which are then crosscorrelated. Strain images are produced by first compensating two-dimensional displacements for lateral motion with lateral motion displacement estimates obtained from the proposed lateral displacement estimation algorithm and then estimating axial displacements. Both phantom and human data experiments show that the proposed method provides better signal-to-noise ratio and contrast-to-noise ratio characteristics than a conventional strain imaging method that utilizes axial displacement estimates only.

• Journal of Digital Contents Society
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• v.19 no.8
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• pp.1603-1615
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• 2018

In order to achieve the low complexity and area, power in the design of Optical Image Stabilization (OIS) suitable for the smart phone, this paper presents the following design explorations, such as; optimization of gyroscope sampling rate, simple and accurate gyroscope filters, and reduced operating frequency of motion compensation, optimized bit width in ADC and DAC, evaluation of noise effects due to PWM driving. In experiments of gyroscope sampling frequencies, it is found that error values are unvaried in the frequency above 5KHz. The gyroscope filter is efficiently designed by combining the Fuzzy algorithm, to illustrate the reasonable compensation for the angle and phase errors. Further, in the PWM design, the power consumption of 2MHz driving is shown to decrease up to 50% with respect to the linear driving, and the imaging noises are reduced in the driving frequency above 2MHz driving frequency. The operating frequency could be reduced to 5KHz in controller and 10KHz in driver, respectively, in the motion compensation. For ADC and DAC, the optimized exploration experiments verify the minimum bit width of 11bits in ADC as well as 10bits in DAC without the performance degradation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.64-70
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• 2008

The H.264 standard is widely used due to the high compression rate and quality. The deblocking filter of the H.264 standard improves the quality of images by eliminating blocking artifacts of pictures, and it requires a lot of computation. We propose a new hardware architecture for the deblocking filter with pipelined architecture, 1-D filters which support both horizontal and vertical filtering and efficient memory management. Four memory blocks are configured for the efficient storage and access of the current macroblock and adjacent referenced sub-macroblocks, and the pixel data from the motion compensation unit can be transferred without waiting during the computation cycles of the deblocking filter. The number of computation cycles and the hardware area are reduced using the proposed architecture, and the performance of the H.264 decoder is improved. We design the deblocking filter using Verilog-HDL and implement using an FPGA. The designed deblocking filter can be used for decoding HD quality images at 77 MHz.

• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.123-132
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• 2011

Recently, DVC (Distributed Video Coding) is receiving a lot of attention as one of the low complexity video encoding techniques suitable for various applications with computation-limited and/or power-limited environment, and is being actively studied for improving the coding efficiency. This paper proposes a rate-distortion based selective block encoding scheme. First, the motion information is obtained in the process of generating side information at decoder and received through the feedback channel, and then, based on this information, the proposed method performs a selective block encoding based on rate-distortion optimization. Experimental results show that the performance of the proposed scheme reaches up to 2.2 dB PSNR gain over the existing scheme. Moreover, it is shown that the complexity can be reduced by encoding parts of region considering rate-distortion cost.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.65-68
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• 2003

블록화 현상은 블록 기반의 부호화와 이에 따른 거친 양자화 계수를 적용할 때 나타날 뿐 아니라 블록화가 나타난 블록을 움직임 보상으로 가져와 적용할 때 이후 영상에 전파되게 된다. 이를 방지하기 위해 H.264/MPEG-4 AVC 표준은 부호화 및 복호화 과정에 동시에 포함된 형태의 루프 필터를 적용하였다. 필터는 블록 경계에서 경계 양쪽의 블록 예측 모드에 기반 한 필터의 세기를 결정하고 양자화 계수를 이용한 한계 값과 화소 값윽 비교하여 블록 경계에 적응적으로 적용한다. 이 때 필터의 특성을 결정하는 편차 값을 부호기에서 전송하게 되는데 이 값은 부호기 구현에 따라 달라질 수 있다. 본 논문은 부호화하는 각 영상의 특성을 정의하고 편차 값을 정함으로써 영상에 적응적인 디블로킹 필터 알고리즘을 구현 및 실험을 통하여 검증한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.20-23
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• 2010

분산 동영상 부호화 시스템에서는 복호기에서 움직임 보상 보간 기법을 이용하여 부가정보를 생성한다. 생성된 부가정보의 정확성이 Wyner-Ziv 프레임을 복원하기 위한 parity 정보량에 큰 영향을 미치기 때문에 부가정보의 정확한 생성이 분산 동영상 부호화 시스템의 성능에 큰 영향을 미친다. 따라서 본 논문에서는 다양한 부가정보 생성 기법의 성능을 분석하고 효율적인 부가정보 생성 기법을 제안하였다. 또한 생성된 부가정보가 분산 동영상 부호화 시스템의 성능에 미치는 영향을 비교분석 하였다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.4
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• pp.39-44
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• 2004

The three-dimensional (3D) wavelet transform with motion compensation is suitable for very high quality video coding due to both spatial and temporal decorrelations. However, it still suffers from image degradation such as ringing artifact and afterimage because of the loss of high frequency components by quantization. This paper proposes an iterative regularized enhancement of the motion-compensated 3D wavelet coded video. We also propose the adaptive implementation of the constraints for the regularization. It selectively suppresses the high frequency component along only the corresponding edge direction.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.31-43
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• 1999

The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.383-393
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• 2010

DVC (Distributed Video Coding) allows us to explore the video statistics at the decoder side, resulting in a less complex encoder and more complex decoder. In this approach, it is important to generate a good prediction to the current Wyner-Ziv frame, called side information, which plays a crucial role in the overall performance of a DVC system. Conventional MCFI (motion compensated frame interpolation) techniques, which explore temporal correlations between neighbor frames of the current frame, preform the block-based or object-based motion estimation, but, they do not include the basis frame for the Wyner-Ziv frame. This paper proposes an efficient way to get better side information, by finding the average frame between neighbor frames and by comparing adaptively the candidate blocks. Through computer simulations, it is shown that the proposed method can improve the performance up to 0.4dB and provide better subjective and objective visual qualities in Wyner-Ziv CODEC.