• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2307-2314
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• 2015

This paper focuses on the generation algorithm of BeiDou pseudorange correction (PRC) and simulation based performance verification for design of Differential Global Navigation Satellite System (DGNSS) reference station and integrity monitor (RSIM) in order to prepare for recapitalization of DGNSS. First of all, it discusses the International standard on DGNSS RSIM, based on the interface control document (ICD) for BeiDou, estimates the satellite position using satellite clock offset and user receiver clock offset, and the system time offset between Global Positioning System (GPS) and BeiDou. Using the performance verification platform interfaced with GNSS (GPS/BeiDou) simulator, it calculates the BeiDou pseudorange corrections , compares the results of position accuracy with GPS/DGPS. As the test results, this paper verified to meet the performance of position accuracy for DGNSS RSIM operation required on Radio Technical Commission for Maritime Services (RTCM) standard.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.436-439
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• 2011

본 논문은 클록 보정회로를 가진 1V 2.56-GS/s 6-bit flash analog-to-digital converter (ADC) 제안한다. 제안하는 ADC 구조에서 아날로그 블록은 단일 T/H와 2단의 프리앰프, 그리고 비교기를 사용된다. 2단의 프리앰프와 비교기의 출력에 옵셋의 크기를 줄이기 위하여 저항 평균화 기법을 적용하였다. 디지털 블록은 quasi-gray rom base 구조를 사용한다. 3입력 voting 회로로 flash ADC에서 발생하기 쉬운 bubble error를 제거하였으며, 고속 동작을 위해 단일 클록을 사용하는 TSPC F/F로 구현한다. 제안하는 flash ADC는 클록 듀티 비를 조절할 수 있는 클록 보정회로를 사용한다. 클록 보정 회로는 비교기 클록 듀티 비를 조절하여 리셋 시간과 evaluation 시간의 비율을 최적화함으로 dynamic 특성을 확보한다. 제안한 flash ADC는 1V 90nm의 CMOS 공정에서 설계되었다. Full power bandwidth인 1.2 GHz 입력에 대하여 ADC 성능을 시뮬레이션을 통해 확인하였다. 설계된 flash ADC의 면적과 전력소모는 각각 $800{\times}400\;{\mu}m^2$와 193.02mW 이다.

• Journal of Navigation and Port Research
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• v.38 no.4
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• pp.373-378
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• 2014

In order to prepare for recapitalization of differential GNSS (DGNSS) reference station and integrity monitor (RSIM) due to GNSS diversification, this paper focuses on differential correction algorithm using GPS/Galileo pesudorange. The technical standards on operation and broadcast of DGNSS RSIM are described as operation of differential GPS (DGPS) RSIM for conversion of DGNSS RSIM. Usually, in order to get the differential corrections of GNSS pesudorange, the system must know the real positions of satellites and user. Therefore, for calculating the position of Galileo satellites correctly, using the equation for calculating the SV position in Galileo ICD (Interface Control Document), it estimates the SV position based on Ephemeris data obtained from user receiver, and calculates the clock offset of satellite and user receiver, system time offset between GPS and Galileo, then determines the pseudorange corrections of GPS/Galileo. Based on a platform for performance verification connected with GPS/Galileo integrated signal simulator, it compared the PRC (pseudorange correction) errors of GPS and Galileo, analyzed the position errors of DGPS, DGalileo, and DGPS/DGalileo respectively. The proposed method was evaluated according to PRC errors and position accuracy at the simulation platform. When using the DGPS/DGalileo corrections, this paper could confirm that the results met the performance requirements of the RTCM.

• The Journal of Engineering Geology
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• v.16 no.4 s.50
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• pp.429-435
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• 2006

A preliminary study was made for density correction for the effect of separation between sonde and borehole wall due to the existence of casing in a borehole. Firstly, series of gamma-gamma measurements were obtained with 3 different separations in 3 different density models constructed in Kangwon National University. Secondly, density correction charts were made based on the 'spine and ribs' technique in mud cake correction. Using these charts, we could determine effectively the true density from the measurement in the thinly cased borehole.

• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.4
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• pp.542-551
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• 1998

In this study, a method of error compensation for channel gain imbalance, phase imbalance and local oscillator leakage in the modulator of frequency direct conversion is suggested. The compensation of channel imbalance can be carried out by using the received power after transmitting test signal. By applying this method, the phase imbalance conversion with frequency can be easily compensated since this method is rarely affected by the transmission channel. It is confirmed that the algorithm proposed in this study(iteration coefficient=11) converges faster than conventional algorithm(iteration coefficient=43). From the numerical results, the DC-offset, channel gain, phase imbalance compensation coefficient and iteration number converges into($f_1$=0.0199999, $f_2$=-0.050001, $C_{22}$=0.9133, $C_{12}$=-0.0524, N=13) when the local oscillator leakage is not considered. However, it converges into($f_1$=-0.02, $f_2$=-2.2476, $C_{22}$=0.9133, $C_{12}$=-0.0524, N=16) when the local oscillator leakage is considered.

• Journal of the Korean Society for Precision Engineering
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• v.34 no.1
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• pp.53-58
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• 2017

A fine stage is developed for the 3-DOF error compensation of a linear axis in order to improve the positioning accuracy. This stage is designed as a planar parallel mechanism, and the joints are based on a flexure hinge to achieve ultra-precise positioning. Also, the effect of Abbe's offsets between the measuring and driving coordinate systems is minimized to ensure an exact error compensation. The mode shapes of the designed stage are analyzed to verify the desired 3-DOF motions, and the workspace and displacement of a piezoelectric actuator (PZT) for compensation are analyzed using forward and inverse kinematics. The 3-DOF error of a linear axis is measured and compensated by using the developed fine stage. A marked improvement is observed compared to the results obtained without error compensation. The peak-to-valley (PV) values of the positional and rotational errors are reduced by 92.6% and 91.3%, respectively.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3100-3102
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• 2000

In this paper, we propose to a robust frequency offset estimation method of OFDM signals. A carrier frequency offset may be decomposed into an integer multiple of the subcarrier spacing and a residual frequency offset. Fractional part of frequency offset is obtained by using the maximum likelihood estimation(MLE) method. And we use the correlation of the samples at the output of the discrete Fourier transform(DFT) to estimate integer part of frequency offset. The result shows that the estimation frequency offset is almost linear to frequency offset. We propose to an improved estimation error variance of the carrier frequency offset estimation. The proposed estimator has better performance than the conventional ones in terms of error variance and tracking range.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.972-983
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• 1996

This paper proposes a new technique for frequency offset correction for OFDM systems on a frequency selective fading channel. Frequency offset in OFDM introduces interchannel interference among the multiple subcarriers of OFDM signal. To compensate the interference, this paper describes an algorithm with two stages:acquisition and tracking. At both stages, the proposed algorithm oversamples the received OFDM signal to obtain a couple of demodulated symbol sets. At acquisition stage the frequency offset is reduced to half or less of the intercarrier spacings by matching the sign pattern of each element of the sets. Next, at tracking stage the frequency offset is corrected with a frequency detector which is controlled by the correlation of the two sets. It is shown that the proposed algorithm can correct the frequency offset in the event of uncertainty in the initial offset that exceeds one half of the intercarrier spacing. In addition, the proposed algorithm is robust to transmitted symbols and channel characteristics by using oversampled symbol sets.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.951-962
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• 2002

A DMT transceiver recovers the sampling time from reserved sub-carriers, the pilots. Since the pilots are available after the FFT, the symbol synchronization must be done before sample synchronization. In DMT VDSL system, symbol synchronization is handled separately from sample synchronization, although the two processes are intimately related. The DMT symbol itself contains sufficient information, the cyclic extension, for symbol synchronization. Using only the sign bit of received signal, the Maximum Likelihood Estimation solution is derived. The Tx windowing in the transmitter of DMT VDSL system results in the blurring of MLE peaks. We propose the weighted summing MLE method using the sign bit which produces the clearly sharp top of MLE peaks. The stability of symbol synchronization is improved significantly by averaging over a few symbols. This paper presents the study of the original MLE and the weighted summing MLE using sign bit. A clock difference between transmitter and receiver destroys the oahogonality of the carriers. Therefore, a receiver using asynchronous sampling must perform timing correction in the discrete-time domain. We introduce an efficient digital sample synchronization method which is based on temporal and frequency domain digital signal processing.