• Title/Summary/Keyword: 오버샘플 신호처리

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Mitigation of Impulse Noise Using Slew Rate Limiter in Oversampled Signal for Power Line Communication (전력선 통신에서 오버 샘플링과 Slew Rate 제한을 이용한 임펄스 잡음 제거 기법)

  • Oh, Woojin;Natarajan, Bala
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.23 no.4
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    • pp.431-437
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    • 2019
  • PLC(Power Line Communication) is being used in various ways in smart grid system because of the advantages of low cost and high data throughput. However, power line channel has many problems due to impulse noise and various studies have been conducted to solve the problem. Recently, ACDL(Adaptive Cannonical Differential Limiter) which is based on an adaptive clipping with analog nonlinear filter, has been proposed and performs better than the others. In this paper, we show that ACDL is similar to the detection of slew rate with oversampled digital signal by simplification and analysis. Through the simulation under the PRIME standard it is shown that the proposed performs equal to or better than that of ACDL, but significantly reduce the complexity to implement. The BER performance is equal but the complexity is reduced to less than 10%.

Design of Over-sampled Channelized DRFM Structure in order to Remove Interference and Prevent Spurious Signal (간섭 제거 및 스퓨리어스 방지를 위한 오버샘플링 된 채널화 DRFM 구조 설계)

  • Kim, Yo-Han;Hong, Sang-Guen;Seo, Seung-Hun;Jo, Jung-Hun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.8
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    • pp.1213-1221
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    • 2022
  • In Electronic Warfare, the need to develop a jamming system that protects our location information from enemy radar is constantly increasing. The jamming system normally uses wide-band DRFM(Digital Radio Frequency Memory) that processes the entire bandwidth at once. However, it is difficult to jam if there is a CW(Continuous Wave) interference signal in the band. Recently, instead of wide-band signal processing, a structure using a filter bank that divides the entire band into several sub-bands and processes each sub-band independently has been proposed. Although it is possible to handle interference signal through the filter bank structure, spurious signal occurs when the signal is received at a boundary frequency between sub-bands. Spurious signal makes a output power of jamming signal distributed, resulting in lower JSR(Jamming to Signal Ratio) and less jamming effect. This paper proposes an over-sampled channelized DRFM structure that enables interference response and prevents spurious signal for sub-band boundary frequency input.

Quality Measurement Algorithm for IS-95 Reverse-link Signal (IS-95 역방향링크 신호의 품질 측정 알고리즘)

  • Kang, Sung-Jin;Kim, Nam-Yong
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.9
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    • pp.3428-3434
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    • 2010
  • In this paper, we proposed and implemented a quality measurement algorithm for IS-95 reverse-link signal. To measure the quality of the received signal, equalization, carrier frequency/phase offset estimation, and timing synchronization are essential. And, all signal processing are carried out with baseband signal. The equalizer works with 4-oversampled samples to remove ICI(InterChip Interference). The frequency/phase offset estimator is followed by timing synchronizer since it can work without aid of data and timing information. As the number of interpolation in timing synchronization increases, the measurement accuracy improves, but computation load increases simultaneously. Therefore, one need to choose adequately the number of interpolation regarding to the platform performance to be used for the proposed algorithm.

Novel Polar Transmitter with 2-Bit Sigma-Delta Modulation (2비트 시그마-델타 변조를 이용한 새로운 폴라 트랜스미터)

  • Lim, Ji-Youn;Cheon, Sang-Hoon;Kim, Kyeong-Hak;Hong, Song-Cheol;Kim, Dong-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.8
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    • pp.970-976
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    • 2007
  • This paper presents a novel polar transmitter architecture with a 2-bit sigma-delta modulator. In the proposed architecture, the 2-bit sigma-delta modulator is introduced to suppress quantization noise of conventional sigma-delta modulator. The power amplifier configuration is also modified in a binary form to accommodate the 2-bit digitized envelope signal. The Ptolemy simulation results of the proposed structure show that the spectral property is greatly improved in full transmit band of EDGE system. The fine quantization scheme of the 2-bit modulator lowers the noise level by 10dB without increasing the over-sampling ratio, which may be obtained if the over-sampling ratio increases twofold. Dynamic range is also enhanced up to 5dB owing to the new form of the power amplifier in the transmitter.

Implementation Factors for Multi-rate Parallel Interference Cancellation in the IMT-2000 3GPP System (IMT-2000 3GPP 시스템을 위한 다중 전송율 병렬형 간섭제거기의 구현 요소들)

  • 김진겸;오성근;선우명훈;김성락
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.40 no.2
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    • pp.56-63
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    • 2003
  • We investigate some implementation factors that affect the performance of multi-rate parallel interference cancellers (PICs) for the international mobile telecommunications-2000 (IMT-2000) 3rd-generation partnership project (3GPP) system. We consider the simple multi-rate PIC [1,2] that can remove effectively multiple access interference (MAI) through block-based detection and sample-based cancellation in asynchronous user environments. The PIC structure has significantly lower complexity as compared with that of the existing scheme, especially as the number of users increases. We analyze the effects of timing error, oversampling rate, unsynchronized users and/or outer-cell interference, and the number of Quantization bits on the PIE performance through extensive computer simulations. The models for such factors and the optimum parameters are drawn. Finally, we evaluate the receiver complexities of the PIC receivers employing using the advanced removal scheme.

Lightweight FPGA Implementation of Symmetric Buffer-based Active Noise Canceller with On-Chip Convolution Acceleration Units (온칩 컨볼루션 가속기를 포함한 대칭적 버퍼 기반 액티브 노이즈 캔슬러의 경량화된 FPGA 구현)

  • Park, Seunghyun;Park, Daejin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.11
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    • pp.1713-1719
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    • 2022
  • As the noise canceler with a small processing delay increases the sampling frequency, a better-quality output can be obtained. For a single buffer, processing delay occurs because it is impossible to write new data while the processor is processing the data. When synthesizing with anti-noise and output signal, this processing delay creates additional buffering overhead to match the phase. In this paper, we propose an accelerator structure that minimizes processing delay and increases processing speed by alternately performing read and write operations using the Symmetric Even-Odd-buffer. In addition, we compare the structural differences between the two methods of noise cancellation (Fast Fourier Transform noise cancellation and adaptive Least Mean Square algorithm). As a result, using an Symmetric Even-Odd-buffer the processing delay was reduced by 29.2% compared to a single buffer. The proposed Symmetric Even-Odd-buffer structure has the advantage that it can be applied to various canceling algorithms.