• The Journal of the Korea Contents Association
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• v.8 no.7
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• pp.75-84
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• 2008

Concurrency and synchronization problems are often caused by database applications concurrently accessing databases managed by DBMS. Most commercial DBMSs support isolation levels to resolve these problems. Verification of isolation levels are most important because consistency and integrity constraints of the database can be violated according to isolation levels of transactions that consists of database applications. We propose a test tool set to verify and reveal faulty settings of isolation levels and implement a prototype of the test tool set. The proposed tool set analyzes the SQL statements of ESQL/C programs, attaches the test codes to verify isolation levels, runs the test transactions and detects errors.

• Journal of IKEEE
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• v.22 no.3
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• pp.800-804
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• 2018

This paper presents a novel HF band differential quadrature phase-shift keying (DQPSK) orthogonal frequency-division multiplexing (OFDM) communication system. The system can deliver 3.6 kbps with a bandwidth of about 3 kHz. In a digital modem, OFDM with 32-point fast Fourier transform is used. In the system, each subcarrier uses DQPSK modulation. Hence, a demodulator does not require carrier phase recovery and symbol timing recovery. And, each subcarrier employs CRC error check code individually. By using CRC code for each subcarrier, bit error caused by multipath fading can be recovered simply.

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06b
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• pp.214-216
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• 2012

BIT(Built-in Test)란 소프트웨어와 하드웨어의 기능 및 상태를 진단하고 오류에 대응하기 위한 방법론으로 빠른 오류 대처가 있어야 하는 다양한 분야에서 사용되고 있다. 현업에서의 BIT는 도메인의 특성에 따라 고려해야 하는 요소가 많으므로 각 도메인에 맞춰 구조화되지 않은 형태로 개발되고 있다. 따라서 기존 개발 방법론은 반복적인 작업이 수반되며 적용 환경 및 상활에 따라 변화하는 부분을 매번 새로 개발하기 위해 많은 인력과 시간이 필요하다는 문제점을 가진다. 이를 해결하기 위하여 본 논문에서는 개선된 BIT 개발 프로세스를 제안한다. 제안하는 프로세스는 BIT 처리 과정을 일반화하여 명세하고 이를 활용하여 BIT 처리 코트를 자동 생성한다. 그리고 BIT 코드를 검증할 수 있는 시뮬레이션 환경을 제공한다. 이를 통해 BIT 처리 구조 개발 과정의 편의성과 생산성을 향상하고 BIT 처리 구조의 유연성과 확장성 그리고 안정성을 높일 수 있다.

• Transactions of The Korea Fluid Power Systems Society
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• v.8 no.3
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• pp.1-7
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• 2011

As the technologies of electronic device have advanced these days, most of mechanical systems are designed with electronic control unit to take advantage of control parameter adaption to operating conditions and firmware flexibilities as well. On-board diagnosis, which detects the system malfunction and identifies potential source of error with its own diagnostic criteria, and fail-safe that can switch the mode of operation in view of recognized error characteristics enables easy maintenance and troubleshooting as well as system protection. This paper dealt with the development of diagnosis and fail-safe function for proportional flow control valve. All type of errors related to valve control system components are investigated and assigned to a specific hexadecimal codes. Cumulative error detection algorithm is applied in order for the sensitivity and reliability to be appropriate. Embedded simulator which runs simultaneously with system program provides the virtual error simulation environment for expeditious development of error detection algorithm. The diagnosis function was verified both with solenoid valve and embedded simulator test and it will enhance the valve control system monitoring function.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.60-65
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• 2009

A highly reliable Video Transmission System (VTS) was developed in order to obtain both video and digital data simultaneously in the real time flight test situation of a flying vehicle. The VTS integrates GPS date digital telemetry data and video signals into a compact digital data package which is compressed and processed by an MPEG-2 Encoder and a modulator respectively. The modulator is composed of a specially devised Forward Error Correction processor and base band QPSK modulator. The designed VTS was verified and proved for its required functioning and performance through separate flight tests using an airplane and Rockets.

• Journal of the Korean Institute of Intelligent Systems
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• v.9 no.5
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• pp.490-495
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• 1999

In this paper. a learning method VoD-EBP for neural networks is proposed, which learn patterns by error back propagation. Based on Voronoi diagram, the method initializes the weights of the neural networks systematically, wh~ch results in faster learning speed and alleviated local optimum problem. The method also shows better the reliability of the design of neural network because proper number of hidden nodes are determined from the analysis of Voronoi diagram. For testing the performance, this paper shows the results of solving the XOR problem and the parity problem. The results were showed faster learning speed than ordinary error back propagation algorithm. In solving the problem, local optimum problems have not been observed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5B
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• pp.526-531
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• 2009

In this paper, we propose new novel technique (ILCT: Instruction-Level Correlation Technique) which can detect tempered instructions by software attacks or hardware attacks before their execution. In conventional works, due to both high complex computation of cipher process and low processing speed of cipher modules, existing secure processor architecture applying cipher technique can cause serious performance degradation. While, the secure processor architecture applying ILCT with FEC does not incur excessive performance decrease by complexity of computation and speed of tampering detection modules. According to experimental results, total memory overhead including parity are increased in average of 26.62%. Also, secure programs incur CPI degradation in average of $1.20%{\sim}1.97%$.

• Journal of KIISE:Databases
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• v.32 no.1
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• pp.86-99
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• 2005

In this paper, we suggest a system which automatically verifies and tunes transaction processing database applications based on program analysis technology. This system automatically verifies two kinds of transaction processing errors. The first case is the un-closed transaction. In this case, data is not updated as expected or performance of overall system can decrease seriously by locking some database tables until the process terminates. The second case is the miss-use of transaction isolation(inking) level. This causes runtime exception or abnormal termination of the program depending on runtime environment. This system automatically tunes two kinds of inefficient definition of transaction processing which decrease the performance of overall system. The first case happens when opened transaction is closed too late. And the second case happens when transaction isolation level is set too high.

• Journal of Drive and Control
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• v.15 no.4
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• pp.30-38
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• 2018

Electronic control units (ECUs) are currently popular, and have evolved further towards the high-end application of autonomous vehicles in the automotive industry. Such digital technologies have also become widespread, in agriculture and construction equipment. Likewise, transmission control of high-speed tracked vehicles is based on the transmission control unit (TCU), performing complex gear change control functions, and diagnostic algorithms (a TCU's self-diagnostic and reporting capability of malfunction data through CAN communication). Since all functions of TCU are implemented by embedded-software, it is hardly possible to analyze specifications by reverse engineering. In this paper a real-time transmission simulator adaptable to TCU is presented, for analysis of diagnosis algorithm and standards. Signal simulation circuits are deliberately designed considering electrical characteristics of TCU inputs and various analysis tools, such as analog input auto scan function, and global output enable switch, are implemented in software. Test results from hardware-in-the-loop simulator verify tolerance time for each error, as well as cause of fault, error reset conditions.