• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.47-52
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• 2009

H.264 video coding standard is widely used due to the high compression rate and quality. The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation and management of the reference pixels. The reference pixels read from external memory using efficient memory management for data reuse is necessary along with the high performance interpolators. We propose the architecture of a motion compensation unit for H.264 decoders. It is composed of 2-dimensional circular register files, a motion vector predictor and high performance interpolators with low complexity. The 2-dimensional circular register files reuse reference pixel data as much as possible, and feed reference pixel data to interpolators without any latency and complex logic circuits. We design a motion compensation unit and a intra-prediction unit and integrate them into a prediction unit and verify the operation and the performance.

• Journal of Korea Multimedia Society
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• v.8 no.8
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• pp.1080-1087
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• 2005

Significant computations for full search (FS) motion estimation have been a big obstacle in real-time video coding and recent MPEG-4 AVC (advanced video coding) standard requires much more computations than conventional MPEG-2 for motion estimation. To reduce an amount of computation of full search (FS) algorithm for fast motion estimation, we propose a new and fast matching algorithm without any degradation of predicted images like the conventional FS. The computational reduction without any degradation in predicted image comes from fast elimination of impossible candidate motion vectors. We obtain faster elimination of inappropriate motion vectors using efficient matching units from localization of complex area in image data and dithering order based matching scan. Our algorithm reduces about $30\%$ of computations for block matching error compared with the conventional partial distortion elimination (PDE) algorithm, and our algorithm will be useful in real-time video coding applications using MPEG-4 AVC or MPEG-2.

• Smart Media Journal
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• v.3 no.4
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• pp.16-21
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• 2014

HEVC is the latest joint video coding standard with ITU-T SG16 WP and ISO/IEC JTC1/SC29/WG11. Its coding efficiency is about two times compared to H.264 high profile. Intra prediction has 35 directional modes including dc and planer. However an accurate mode decision on lots of modes with SSE is too costly to implement it with hardware. The key idea of this paper is a DCT shared architecture to reduce the complexity of HEVC intra encoder. It is to use same DCT block to quantize as well as to calculate SSE in RDO. The proposed intra encoder uses two step mode decision to lighten complexity with simplified RDO blocks and shares the transform resources. Its BD-rate increase is negligible at 20% on hardware aspect and the operating clock frequency is 300MHz@60fps on FHD ($1920{\times}1080$) image.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.5
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• pp.151-161
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• 2009

Audio Video Standard (AVS) is the audio and video compression standard that was developed for domestic video applications in China. AVS employs low complexity tools to minimize degradation of RD performance of the state-the-art video codec, H.264/AVC. The AVS video codec consists of $8{\times}8$ block prediction and the same size transform to improve compression efficiency for VGA and higher resolution sequences. Currently, the AVS has been adopted more and more for IPTV services and mobile applications in China. So, many consumer electronics companies and multimedia-related laboratories have been developing applications and chips for the AVS. In this paper, we implemented the AVS video decoder and optimize it on TI's Davinci EVM DSP board. For improving the decoding speed and clocks, we removed unnecessary memory operations and we also used high-speed VLD algorithm, linear assembly, intrinsic functions and so forth. Test results show that decoding speed of the optimized decoder is $5{\sim}7$ times faster than that of the reference software (RM 5.2J).

• Journal of Broadcast Engineering
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• v.13 no.1
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• pp.137-151
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• 2008

H.264/AVC is showed high coding efficiency more than previous video coding standard by using new coding tools. Specially, Variable block-based motion estimation and Rate-Distortion Optimization are very important coding tools in H.264/AVC. These coding tools have high coding efficiency, however the encoder complexity greatly increase due to these coding tools. In this paper, we propose early SKIP mode decision and selective inter/intra mode decision to reduce the computational complexity. Simulation results show that the proposed method could reduce encoding time of the overall sequences by 30% on average than JM 10.2 without noticeable degradation of coding efficiency. Besides, the proposed method runs over twice as fast as the previous proposed Fast Coding Mode Selection method (FCMS)[5].

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.2
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• pp.30-38
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• 2002

In this paper, we propose a new method for image coding which efficiently use the relationship between the properties of spatial image and its wavelet transform. Firstly, an original image is decomposed into several layers by the wavelet transform, and simultaneously decomposed into 2$^n$$\times$2$^n$blocks. Each block is classified into two regions according to their standard deviation, i.e., low activity region(LAR) and high activity region(HAR). The region with low frequency in spatial domain does not only appears as zero regions in wavelet frequency domain like HL, LH, and HH but also gives little influence to the quality of reconstructed image. The other side, the high frequency regions are related to significant coefficients which gives much influence to image reconstruction. In this paper, we propose a image coding method to obtain high compression rate at low bit rate by these properties. The LAR region is encoded by LAR coding method which is proposed in this paper, the HAR by a technique similar to bitplane coding in hierarchical tree. Simulation results show that th,$\boxUl$ proposed coding method has better performance than EZW and SPIHT schemes in terms of image quality and transmitted bit rates, can be successfully applied to the application areas that require of progressive transmission.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1485-1490
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• 2005

Variable length code is an integral component of many international standards on image and video compression currently. Context-based Adaptive Variable Length Coding(CAVLC) is adopted by the emerging JVT(also called H.264, and AVC in MPEG-4). In this paper, we design an architecture for CAVLC encoder, including a coeff_token encoder, level encoder, total_zeros encoder and run_before encoder. The designed CAVLC encoder can encode one syntax element in one clock cycle. As a result of implementation by Vertex-1000e of Xilinx, its operation frequency is 68MHz. Therefore, it is very suitable for video applications that require high throughput.

• Journal of Broadcast Engineering
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• v.7 no.4
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• pp.317-326
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• 2002

The adaptive coding schemes in H.264 standardization provide a significant ceding efficiency and some additional features like error resilience and network friendliness. The variable block size motion compensation using multiple reference frames is one of the key H.264 coding elements to provide main performance gain, but also the main culprit that increases the overall computational complexity. For this reason, this paper proposes a selective motion estimation algorithm based on variable block size for fast motion estimation in H.264. After we find the SAD(Sum of Absolute Difference) at initial points using diamond search, we decide whether to perform additional motion search in each block. Simulation results show that the proposed method is five times faster than the conventional full search in case of search range $\pm$32.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.343-346
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• 2003

본 논문에서는 최신 동영상 압축 표준 규격 H.264에서 화면 간 예측 부호화시 참조 화면 수가 제한되어 있을 때 부호화 효율을 최대화할 수 있는 적웅적 참조 화면 선택 기법을 제안하였다. 참조 화면 선택 시 시간적인 거리를 우선시 하는 현재 방식은 부호화 효율 측면에서 최적의 선택과는 거리가 있다. 따라서 참조 화면 선택에 있어서 실시간 온라인 상황을 가정하고 부가적인 계산을 최소화하는 것을 조건으로 했을 때 대표 화면과의 간접 비교를 통하여 현재 참조 화면들 간 상호 유사성이 가장 큰 화면을 제외하는 방법을 통해 문제를 해결하고자 하였다. 화면 간 예측 부호화 시 참조 화면 간 중복되는 요소를 최대한 줄이는 방향으로 참조 화면을 선택해 나감으로서 참조되는 샘플들을 다양화할 수 있다. 참조 화면 간 상호 유사성 판별은 대표 화면과 각 참조 화면 간 움직임 정보를 고려해 화면 간 부호화시 계산되는 8*8 블록의 R-D 비용함수 값을 사용하였다. 실험 결과 기존의 슬라이딩 윈도우 방식을 이용한 참조 화면 선택 방법에 비해 부가적인 계산이 거의 없이 부호화 효율의 개선이 있었으며 그 개선 정도는 기존의 방식에서 참조 화면을 $1{\sim}2$장 더 사용한 결과와 같았다. 이는 기존의 방법에 의해 참조 화면을 선택할 경우 나타나는 참조 화면 간 중복성을 줄였기 때문이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.45-51
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• 2003

JPEG200, a new international standard for still image compression based on wavelet and bit-plane coding techniques, is developed. In this paper, we design the DWT(Discrete Wavelet Transform) and quantizer for JPEG2000 CODEC. DWT handles both lossy and lossless compression using the same transform-based framework: The Daubechies 9/7 and 5/3 transforms, and quantizer is implemented as SQ(Scalar Quantization). The architecture of the proposed DWT and SQ are synthesized and verified using Xilinx FPGA technology. It operates up to 30MHz, and executes algorithms of wavelet transform and quantization for VGA 10 frame per second.