• Journal of KIISE:Computer Systems and Theory
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• v.33 no.1_2
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• pp.62-68
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• 2006

The important arithmetic operations over finite fields include multiplication and exponentiation. An exponentiation operation can be implemented using a series of squaring and multiplication operations over GF($2^m$) using the binary method. Hence, it is important to develop a fast algorithm and efficient hardware for multiplication. This paper presents an efficient bit-serial systolic array for MSB-first multiplication in GF($2^m$) based on the polynomial representation. As compared to the related multipliers, the proposed systolic multiplier gains advantages in terms of input-pin and area-time complexity. Furthermore, it has regularity, modularity, and unidirectional data flow, and thus is well suited to VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.594-600
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• 2002

A data manipulation unit capable of bit partitioned shift and various multimedia data type conversions in addition to conventional shift, is presented. Utilizing the similarity between the data type conversion and the shift, the addition of small amount of interconnections to conventional barrel shifter enables data type conversion as well as shift operations with minimal hardware overhead. The presented data manipulation unit is composed of the shifter block for conventional shift and a pack and a unpack block. It has been designed with verilog HDL and the VLSI implementation results using compass 0.6 um standard cell are discussed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.1
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• pp.39-44
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• 2005

Scheduling for digital system synthesis is assigning each operation in a control/data flow graph(CDFG) to a specific control step without violating precedence relation. It is one of the most important tasks due to its direct influence on the performance of the hardware synthesized. In this paper, we propose a resource-constrained scheduling algorithm. Our algorithm first analyzes the given CDFG to determine the number of functional units of each type, then assigns each operation to a control step while satisfying the constraints. It also tries to improve the solution iteratively by adjusting the number of functional units using the results collected from the previous scheduling. Experiments were performed to test the performance of the proposed algorithm, and results are presented

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.5
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• pp.620-626
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• 1999

캐리-세이브 가산기는 (CSA)는 실제 산업체에서 회로를 설계할 때 연산수식의 계산을 빠르게 처리하기위해 가장 많이 사용되는 구성요소들 가운데 하나이다. [3]의 자료에 의하면 실제 회로 설계에서 나오는 전형적인 연산식에 CSA를 이용했을 때 그렇지 않은 경우보다 최대 54%의 연산처리속도와 42%의 회로 면적 향상을 갖는다고 보고하고 있다. 그러나, 이는 그 연산식이 하나의 설계 블록(sub-design)에 포함되어 있다는 전제하에 도출된 것이다. 회로 설계 규모와 복잡도가 큰 응용이 많아지는 상황에서 설계 블록단위의 계층적 설계는 필수적인 추세이므로, CSA를 이용한 회로 최적화를 실현하기위해서는 설계 블록들간에 걸쳐있는 연산식에 대한 CSA 최적화 또한 매우 중요한 문제이다. 이를 해결하기위해서 이 논문에서는 auxiliary port라는 개념을 이용하여 설계 블록들간의 연산식에 대한 CSA 최적화 방법을 제안한다. 실제 실험에서 우리가 제안한 기법은 회로의 전체적인 영역에 걸쳐 CSA를 적용하는 데 매우 효과적이었으며, 이 기법을 적용하지 않고 얻은 CSA 최적화 회로와 비교했을 때 회로에서의 연산식 계산속도와 그 회로 면적이 상당히 향상되었음을 확인하였다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.10
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• pp.2553-2561
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• 1997

In this paper, a hardware architecture to calculate straight-line Hough transform algorithm for image recognition is suggested. This processor consists of the filtering module for gradient calculation and the HT calculation module, and the angle information are stored in memory table. For the suggested architecture, firstly, algorithm simulation is executed using C language to confirm the operation and to decide the precision of calculation, and secondly, architecture simulation is executed using VHDL language for the total blocks. According to C & VHDL simulation results, it is confirmed that the calculated data value is similarly obtained and the calculation defference is decreased as image clarity and bits increase.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.11a
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• pp.84-86
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• 2018

요즘 자율주행과 같은 최신 기술의 발전과 더불어 촬영된 영상 장면에 대한 깊이있는 이해가 필요하게 되었다. 특히, 기계학습 기술이 발전하면서 카메라로 찍은 영상에 대한 의미론적 분할 기술에 대한 연구도 활발히 진행되고 있다. FuseNet은 인코더-디코더 구조를 이용하여 장면 내에 있는 객체에 대한 의미론적 분할 기술을 적용할 수 있는 신경망 모델이다. FuseNet은 오직 RGB 입력을 받는 기존의 FCN보다 깊이정보까지 활용하여 RGB 정보를 기반으로 추출한 특징지도와의 요소합 연산을 통해 멀티 모달 구조를 구현했다. 의미론적 분할 연구에서는 객체의 전역 컨텍스트가 고려되는 것이 중요한데, 이를 위해 여러 계층을 깊게 쌓으면 연산량이 많아지는 단점이 있다. 이를 극복하기 위해서 기존의 합성곱 방식을 벗어나 새롭게 제안된 팽창 합성곱 연산(Dilated Convolution)을 이용하면 객체의 수용 영역이 효과적으로 넓어지고 연산량이 적어질 수 있다. 본 논문에서는 컨볼루션 연산의 새로운 방법론적 접근 중 하나인 팽창된 합성곱 연산을 이용해 의미론적 분할 연구에서 새로운 멀티 모달 네트워크의 성능 향상 방법을 적용하여 계층을 더 깊게 쌓지 않더라도 파라미터의 증가 없이 해상도를 유지하면서 네트워크의 전체 성능을 향상할 수 있는 최적화된 방법을 제안한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.3-11
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• 2000

In this paper, we design modular multiplication systolic array and exponentiation processor having n bits message black. This processor uses Montgomery algorithm and LR binary square and multiply algorithm. This processor consists of 3 divisions, which are control unit that controls computation sequence, 5 shift registers that save input and output values, and modular exponentiation unit. To verify the designed exponetion processor, we model and simulate it using VHDL and MAX+PLUS II. Consider a message block length of n=512, the time needed for encrypting or decrypting such a block is 59.5ms. This modular exponentiation unit is used to RSA cryptosystem.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.473-480
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• 2021

To achieve the high-speed implementation of post-quantum cryptography, primitive operations should be tailored to the architecture of the target processor. In this paper, we present the optimized implementation of multiplier operation on RISC-V processor for post-quantum cryptography. Particularly, the column-wise multiplication algorithm is optimized with the primitive instruction of RISC-V processor, which improved the performance of 256-bit and 512-bit multiplication by 19% and 8% than previous works, respectively. Lastly, we suggest the instruction extension for the high-speed multiplication on the RISC-V processor.

• Journal of Educational Research in Mathematics
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• v.22 no.4
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• pp.477-494
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• 2012

This study is to review the content organization and developmental ways of the unit on the mixed calculations and explore the alternatives on the basis of students' responsive examples and error patterns with relation to the mixed calculations, mnemonics of PEMDAS and historical context with relation to the order of operations. Then I analyzed the textbook and manual for teachers of the unit of mixed calculations of fourth grade and improvement about teaching the mixed calculations. First, I pointed out illogical connection between practical problem and rules of order of operations. Second, I suggested constructing a textbook by considering conventional character of order of operations. Third, I pointed out the importance of structural understanding of an expression of mixed calculations and various strategies with relation to teaching and learning. This study is suggestive for textbook development of the mixed calculations.