• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.773-781
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• 2013

The Hough transform for line detection is widely used in many machine vision applications due to its robustness against data loss and distortion. However, it is not appropriate for real-time embedded vision systems, because it has inefficient computation structure and demands a large number of memory accesses. Thus, this paper proposes an improved voting scheme of the Hough transform, and then applies this scheme to a Hough transform hardware architecture so that it can provide real-time performance with less hardware resource. The proposed voting scheme reduces computation overhead of the voting procedure using correlation between adjacent pixels, and improves computational efficiency by increasing reusability of vote values. The proposed hardware architecture, which adopts this improved scheme, maximizes its throughput by computing and storing vote values for many adjacent pixels in parallel. This parallelization for throughput improvement is accomplished with little hardware overhead compared with sequential computation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.352-358
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• 2004

This paper is studied the improvement of performance for moving picture encoder using H.263. This is used the new motion vector search algorithm using a relation with neighborhood search point and is applied the integer DCT for the encoder. The integer DCT behaves DCT by the addition operation of the integer using WHT and a integer lifting than conventional DCT that needs the multiplication operation of a floating point number. Therefore, the integer Dn can reduce the operation amount than basis DCT with having an equal PSNR. The new motion vector search algorithm is showed almost similar PSNR as reducing the operation amount than the conventional motion vector search algorithm. To experiment a compatibility of the integer DCT and the conventional DCT, according to result compare case that uses a method only and case that uses the alternate two methods of the integer DCT or the conventional DCT to H.263 encoder and decoder, case that uses the alternate two methods is showed doing not deteriorate PSNR-and being each other compatible visually than case that uses an equal method only.

• Journal of KIISE:Databases
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• v.36 no.1
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• pp.1-7
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• 2009

Flash memory has its unique characteristics: i.e., (1) the write operation is much more costly than the read operation. (2) In-place updating is not allowed. In this paper, we first analyze how these characteristics affect the performance of record management in flash memory, and discuss the problems with previous methods for record management when they are applied to flash memory environment. Next, we propose a new record management method to be suitable for flash memory environment. The proposed method employs a new concept of a container that makes it possible to overwrite data on flash memory several times when performing insertions, deletions, and modifications of records. As a result, this method reduces the number of overwrite operations, and consequently does the number of erase operations. The results of experiments show that our method improves the performance by up to 34%, compared with the previous one.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.4
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• pp.293-304
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• 2005

In this paper, we research on job migration in a grid computing environment with cactus and MPICH-C2 based on Globus. Our concepts are to perform job migration by finding the site with plenty of computational resources that would decrease execution time in a grid computing environment. The Migration Manager recovers the job from the checkpointing files and restarts the job on the migrated site. To select a migrating site, the proposed method considers system's performance index, cpu's load, network traffic to send migration job tiles and the execution time predicted on a migration site. Then it selects a site with maximal performance gains. By selecting a site with minimum migration time and minimum execution time. this approach implements a more efficient grid computing environment. The proposed method Is proved by effectively decreasing total execution time at the $K\ast{Grid}$.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.5
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• pp.510-519
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• 2002

The OpenGIS Consortium has proposed a new web-mapping technology to support interoperability in web GIS environment by developing the specifications of MapServer and GML. In this environment, the MapServer transforms legacy spatial data into GML data, and clients display them on standard web browsers. This web-mapping testbed proposes methods for discovering, accessing, integrating and displaying GIS information except processing of spatial operations which are essential services in GIS environment. This paper proposes the method for executing spatial operations on GML data which are overlays of different map layers in legacy data servers. To support spatial operations on GML data in web GIS environment, this paper designs and implements GDOM based on the W3C's DOM Specifications and OGC's Simple Features Specifications. This paper shows the specifications and implementation of GDOM and the process of spatial operations in web-mapping testbed environment.

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.57-66
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast Fourier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi-valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like ［0,1,2,3］. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used as LUT(Look Up Table) Finally, for the compatibility with the binary system, multiple-valued hybrid-type FFT processor was proposed and designed using binary-four valued encoder, four-binary valued decoder, and the electric current mode CMOS circuit.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.9
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• pp.617-625
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• 2009

NAND flash memory is widely used in embedded systems because of many attractive features, such as small size, light weight, low power consumption and fast access speed. However, it requires garbage collection, which includes erase operations. Erase operation is very slow. Besides, the number of the erase operations allowed to be carried out for each block is limited. The proposed garbage collection method focuses on minimizing the total number of erase operations, the deviation value of each block and the garbage collection time. NAND flash memory consists of pages of three types, such as valid pages, invalid pages and free pages. In order to achieve above goals, we use a page rate to decide when to do garbage collection and to select the target victim block. Additionally, We implement allocating method and group management method. Simulation results show that the proposed policy performs better than Greedy or CAT with the maximum rate at 82% of reduction in the deviation value of erase operation and 75% reduction in garbage collection time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1650-1657
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• 2007

In this paper, we propose an Overlapped Block and an Hanning Window to prevent a Block Discontinuity when we use an algorithm to eliminate ringing artifact which is based on a block structure. The algorithm to eliminate ringing artifact operates with a block structure and 24-RGB data and is based on a modified K-means algorithm. The proposed overlapped block method is piled up one on another per an half of the size of unit-block when an input image is split into several unit-blocks. Therefore, we define a data unit as the unit-block of the block size, $16{\times}16$ pixels. We reconstruct the processed data units into the original form of input image by using an isotropic form of Hanning Window. Finally, in order to evaluate the performance of the abovementioned algorithms, we compare three image, an input image with ringing artifact, an image result obtained by conventional method (non-overlapped), and an image result obtained the proposed method.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.2
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• pp.287-297
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• 2019

When cryptographic algorithms are implemented to provide countermeasures against the side-channel analysis, designers frequently employ the combined countermeasures between the first-order masking scheme and hiding schemes. Their combination can be enough to offer security and efficiency. However, if dummy operations can be distinguished from real operations, an attacker can extract the secret key with lower complexity than the intended attack complexity by the designer inserting the dummy operations. In this paper, we categorize types of variables used in a dummy operation when C language is employed. Then, we present the novel vulnerability that can distinguish dummy operations for all cases where the hiding schemes are applied using different types of variables. Moreover, the countermeasure is provided to prevent the novel vulnerability.

• Journal of IKEEE
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• v.25 no.1
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• pp.174-179
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• 2021

An Edwards curve cryptography (EdCC) core supporting point scalar multiplication (PSM) on Edwards curves of Edwards25519 and Edwards448 was designed. For area-efficient implementation, finite field multiplier based on word-based Montgomery multiplication algorithm was designed, and the extended twisted Edwards coordinates system was adopted to implement point operations without division operation. As a result of synthesizing the EdCC core with 100 MHz clock, it was implemented with 24,073 equivalent gates and 11 kbits RAM, and the maximum operating frequency was estimated to be 285 MHz. The evaluation results show that the EdCC core can compute 299 and 66 PSMs per second on Edwards25519 and Edwards448 curves, respectively. Compared to the ECC core with similar structure, the number of clock cycles required for 256-bit PSM was reduced by about 60%, resulting in 7.3 times improvement in computational performance.