• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.70-79
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• 2013

Recently, there has been introduced various types of pairing computations to implement ID based cryptosystem for mobile ad hoc network. The Miller algorithm is the most popular algorithm for the typical pairing computation such as Weil, Tate and Ate. In this paper, we analyze the feasibility of concrete data fault injection attack, which was proposed by Whelan and Scott, in terms of regardless of round positions during the execution of the Miller algorithm. As the simulation results, the proposed attack that can be employed to regardless of round positions and coordinate systems is effective and powerful.

• Journal of IKEEE
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• v.20 no.4
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• pp.420-423
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• 2016

In this paper, we proposed an implementation of panoramic image stitching that operates in real time at the embedded environment by applying ROI based PROSAC algorithm using the directionality of the image. The conventional panoramic image stitching applies SURF or SIFT algorithm which contains unnecessary computation and a lots of data to detect feature points. In this paper, we use the direction of the input image and we proposed the method of reducing the unnecessary computation by using ROI. We use a gyro sensor and an acceleration sensor. Output data from gyro and acceleration sensors can be calibrated by complementary filter. The calibration does not affect the operating time of the proposed image stitching algorithm in embedded environment. Therefore, it is possible to operate in real-time.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.4
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• pp.143-148
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• 2017

Flash Memory which is light and strong external shock as storage of small electronics like smartphone, digital camera, car black box has been widely used. Since the operation speed of the read operation and the write operation are different from each other, and the flash memory has the feature that it is not possible to overwrite, the delete operation is added to solve these problems. Wear-leveling must also be considered, since the number of erase times of the flash memory is limited. Many studies have been conducted on the substitutional algorithms of flash memory based on these characteristics of recent flash memories. So, to solve the problem that has existing buffer replacement algorithm this thesis divide page into 6 groups and when proposed algorithm select victim page, it consider reference page frequency and page recency.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.36-41
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• 2016

LDPC code has beend applied in recent communication standards, such as Wi-Fi, WiGig, 10GBased-T Ethernet as a forward error correction code. However, LDPC code is required a large amount of computational complexity due to large iterations and block lengths for high performances. To solve this problem, various research has been continously performed for reducing computational complexity. In this paper, we propose AFC algorithm to deactive the variable and check node for reduce the computational complexity.

• Journal of Broadcast Engineering
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• v.18 no.4
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• pp.609-618
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• 2013

This paper proposes a fast image segmentation method that gives high segmentation performance as graph-cut based methods. Graph-cut based image segmentation methods show high segmentation performance, however, the computational complexity is high to solve a computationally-intensive eigen-system. This is because solving eigen-system depends on the size of square matrix obtained from similarities between all pairs of pixels in the input image. Therefore, the proposed method uses the small-size square matrix, which is obtained from all the similarities among regions obtained by segmenting locally an image into several regions by graph-based method. Experimental results show that the proposed multi-scale image segmentation method using the algebraic multi-grid shows higher performance than existing methods.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.61-66
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• 2013

In this paper, we propose an iterative soft dimension reduction based multi-input multi-output (MIMO) detection for coded spatial multiplexing system. In spite of better performance of iterative MIMO detection, its computational complexity gives a significant burden to the receivers. To mitigate this problem, we propose a scheme employing all ordering successive interference cancellation (AOSIC) for hard-decision detection and dimension reduction soft demodulator (DRSD) with iterative decoding for soft-decision detectors, respectively. This scheme can reduce complexity of iterative soft MIMO detection and provide better performance than other conventional detectors.

• Journal of IKEEE
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• v.24 no.3
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• pp.685-690
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• 2020

We propose an efficient convolutional neural network with much lower computational complexity and higher accuracy based on MobileNet V2 for mobile or edge devices. The proposed network consists of bottleneck layers with larger expansion factors and adjusted number of channels, and excludes a few layers, and therefore, the computational complexity is reduced by half. The performance the proposed network is verified by measuring the accuracy and execution times by CPU and GPU using ImageNet100 dataset. In addition, the execution time on GPU depends on the CNN architecture.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.175-181
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• 2010

In this paper, we propose a novel hardware architecture for Rate control module for real time full HD video compression. In the proposed architecture, QP is updated by using the rate control algorithm to every the macroblock line(120MB for Full HD, 20MB for CIF image). Since there are many complex arithmetic and floating point arithmetic in rate control algorithm of JM for H.264, it is impossible to process the rate control algorithm using the integer arithmetic CPU core. So we adopted floating point arithmetic unit in our architecture, and implemented the rate control algorithm using the floating unit. With this implemented hardware, the implemented hardware is verified to be operated in real time.

• Journal of the Korea Computer Industry Society
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• v.3 no.2
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• pp.149-158
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• 2002

This paper deals with design and verification of an arithmetic logic unit(ALU) to be used for development of optical computers. The ALU is based on optical switching device, $LiNbO_3$, which is easy to interface with electronic technology and most common in the market. It consists of an arithmetic/logic circuit performing logic operations, memory devices storing operands and the results of operations, and supplementary circuits to select instruction codes, and operates in bit-serial manner. In addition, a simulator is developed for verification of the design, and a set of basic instructions are executed in sequence and step-by-step changes in the accumulator and the memory are examined through simulations, to show that various operations are performed correctly.

• Journal of KIISE:Software and Applications
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• v.34 no.6
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• pp.503-518
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• 2007

Normalization transforms one parent genotype to be consistent with the other before crossover. In this paper, we explain how normalization alleviates the difficulties caused by non-synonymously redundant encodings in genetic algorithms. We define the encodings with maximally non-synonymous property and prove that the encodings induce uncorrelated search spaces. Extensive experiments for a number of problems show that normalization transforms the uncorrelated search spaces to correlated ones and leads to significant improvement in performance.