• Journal of KIISE:Computer Systems and Theory
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• v.30 no.11
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• pp.663-674
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• 2003

Bump mapping is a technique that represents the detailed parts of the object surface, such as a perturberance of the skin of a peanut, using the geometry mapping without complex modeling. However, the hardware implementation for bump mapping is considerable, because a large amount of per pixel computation, including the normal vector shading, is required. In this paper, we propose a new bump mapping algorithm using the polar coordinate system and its hardware architecture. Compared with other existing architectures, our approach performs bump mapping effectively by using a new vector rotation method for transformation into the reference space and minimizing illumination calculation. Consequently, our proposed architecture reduces a large amount of computation and hardware requirements.

• 전자공학회논문지 IE
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• v.44 no.3
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• pp.12-22
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• 2007

In this paper, we designed of the high speed digital neuron processor in order to digital neural networks. we designed of the MAC(Multiplier and Accumulator) operation unit used residue number system without carry propagation for the high speed operation. and we implemented sigmoid active function which make it difficult to design neuron processor. The Designed circuits are descripted by VHDL and synthesized by Compass tools. we designed of MAC operation unit and sigmoid processing unit are proved that it could run time 19.6 nsec on the simulation and decreased to hardware size about 50%, each order. Designed digital neuron processor can be implementation in parallel distributed processing system with desired real time processing, In this paper.

• Journal of Korea Game Society
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• v.9 no.2
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• pp.135-142
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• 2009

Mesh denoising is a method to remove noise applying various filters. However, those methods usually spend much time since filtering is performed on CPU. Because GPU is specialized for floating point operations and faster than CPU, real-time processing for complex operations is possible. Especially mesh denoising is adequate for GPU parallel processing since it repeats the same operations for vertices or triangles. In this paper, we propose mesh denoising algorithm based on bilateral filtering using GPU parallel processing to reduce processing time. It finds neighbor triangles of each vertex for applying bilateral filter, and computes its normal vector. Then it performs bilateral filtering to estimate new vertex position and to update its normal vector.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.3
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• pp.126-131
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• 2014

In this study, QRS complex is detected by Wavelet Transform and it can be worked in 32bit fixed point operation thought optimization. First, ECG signal is passed though band pass filter. Second, it is transformed using one-band combined wavelet function from 3-band wavelet function. Third, it is passed though moving window integral. Finally, QRS complex is detected by decision rule. The proposed algorithm is evaluated using MIT-BIH arrhythmia database. Its all of process make progress 32-bit fixed-point operation and it makes table that high complexity operations like trigonometrical function. The detection algorithm evaluate through computer simulation.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.4
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• pp.283-290
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• 2009

The rank/select data structure is a basic tool of succinct representations for several data structures such as trees, graphs and text indexes. For a given string sequence, it is used to answer the occurrence of characters up to a certain position. In previous studies, theoretical rank/select data structures were proposed, but they didn't support practical operational time and space. In this paper, we propose a simple solution for implementing rank/select data structures efficiently. According to experiments, our methods without complex encodings achieve nH$_0$ + O(n) bits of theoretical size and perform rank/select operations faster than the original HSS data structure.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.4
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• pp.625-634
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• 2006

In this paper, an efficient and fast algorithm to reduce calculation amount of FIR(Finite Impulse Responses) filtering is proposed. Proposed algorithm enables arbitrary size of parallel processing, and their structures are also easily derived. Furthermore, it is shown that the number of multiplication/sample is remarkably reduced. For theoretical improvement, numbers of sub filters are compared with those of conventional algorithm. In addition to the theoretical improvement, it is shown that number of element for hardwired implementation are reduced comparison to those of the conventional algorithm.

• Journal of Korea Multimedia Society
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• v.10 no.7
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• pp.838-845
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• 2007

In this paper, we propose a modified cubic convolution scaler for the enlargement or reduction of digital images. The proposed method has less computational complexity than the cubic convolution method. In order to reduce the computational complexity, we use the linear function of the cubic convolution and the difference value of adjacent pixels for selecting interpolation methods. We employ adders and barrel shifts to calculate weights of the proposed method. The proposed method is compared with the conventional one for the computational complexity and the image quality. It has been designed and verified by HDL(Hardware Description Language), and synthesized using Xilinx Virtex FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8C
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• pp.598-604
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• 2008

The hold-type display panel such as a liquid crystal displays(LCD) has problem of motion blur. The problem can be improved by a Frame Rate-up Conversion(FRC) using a frame interpolation. We propose a Motion Estimation(ME) by using adaptively expanded block based on frame difference for PRC. The proposed method is executed using an adaptively expanded block in order to get more accurate motion vector. By using frame difference, we can reduce complexity more significantly than conventional methods. We use quantitative analysis in order to evaluate experimental results. The results show that the proposed method has better performance and lower complexity than conventional methods.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.2
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• pp.212-216
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• 2010

Dynamic Thermal Management (DTM) degrades the processor performance for lowering temperature. For this reason, reducing the peak temperature on microprocessors can improve the performance by reducing the performance loss due to DTM. In this study, we analyze various unit selection techniques for computation migration. According to our simulation results, dynamic computation migration based on the thermal difference between the units shows best performance among compared models.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.8
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• pp.763-767
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• 2008

In this paper, to make a high performance and low power CORDIC architecture for 3D operations in mobile devices, we suggest two off-line vectoring algorithms named Angle Based Search (ABS) and Scaling Considered Search (SCS). The ABS algorithm represents a 3D vector with two angles and those angles are used as a condition for searching CORDIC rotation sequences. The SCS algorithm determines the best CORDIC rotation sequence in advance to eliminate extra scaling computation. Using the proposed algorithms, we can observe 50% of latency is reduced. Furthermore, we perform a simple analysis and discuss possible reduction of power consumption by applying voltage scaling method together with the proposed algorithm.