• Journal of KIISE:Databases
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• v.37 no.3
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• pp.171-175
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• 2010

This paper analyzes the tag data inconsistency problem caused by incomplete execution of the tag access operation to the RFID tag's memory and proposes a protocol to control consistent tag data accesses with finalizing the incomplete operation. Passive RFID tag cannot guarantee complete execution of the tag access operations because of uncertainty and unexpected disconnection of RF communications. This leads to the tag data inconsistency problem. To handle this, we propose a concurrency control protocol which defines incomplete tag operations as continuous queries and monitors the tags're-observation continuously. The protocol finalizes the incomplete operation when the tag is re-observed while it blocks inconsistent data accesses from other operations. We justify the proposed protocol by analyzing the completeness and consistency. The experiments show that the protocol shows better performance than the traditional lock-based concurrency control protocol.

• Journal of the Korea Society of Computer and Information
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• v.11 no.3
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• pp.141-149
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• 2006

In this paper, we introduce an improved algorithm for computing matrix triple product that commonly arises in primal-dual optimization method. In computing $P=AHA^{t}$, we devise a single pass algorithm that exploits the block diagonal structure of the matrix H. This one-phase scheme requires fewer floating point operations and roughly half the memory of the generic two-phase algorithm, where the product is computed in two steps, computing first $Q=HA^{t}$ and then P=AQ. The one-phase scheme achieved speed-up of 2.04 on Intel Itanium II platform over the two-phase scheme. Based on memory latency and modeled cache miss rates, the performance improvement was evaluated through performance modeling. Our research has impact on performance tuning study of complex sparse matrix operations, while most of the previous work focused on performance tuning of basic operations.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.183-191
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• 2023

Cryptographic algorithms require extensive computational resources and rely on complex mathematical principles for security. However, IoT devices have limited resources, leading to insufficient computing power. As a result, lightweight cryptography has emerged, which uses fewer computational resources. NIST organized a competition to standardize lightweight cryptography and TinyJAMBU, one of the algorithms in the competition, is a permutation-based algorithm that repeats many permutation operations. In this paper, we implement TinyJAMBU on an 8-bit AVR processor with a proposedtechnique that includes a reverse shift method and precomputing some operations in a fixed key and nonce environment. Our techniques showed a maximum performance improvement of 7.03 times in permutation operations and 5.87 times in the TinyJAMBU algorithm, improving up to 9.19 times in a fixed key and nonce environment.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.2
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• pp.417-426
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• 2024

In general, the implementation of machine learning requires prior knowledge and experience with deep learning models, and substantial computational resources and time are necessary for data processing. As a result, machine learning encounters several limitations when deployed on embedded processors. To address these challenges, this paper introduces a novel approach where a genetic algorithm is applied to the convolution operation within the machine learning process, specifically for performing a selective convolution operation.In the selective convolution operation, the convolution is executed exclusively on pixels identified by a genetic algorithm. This method selects and computes pixels based on a ratio determined by the genetic algorithm, effectively reducing the computational workload by the specified ratio. The paper thoroughly explores the integration of genetic algorithms into machine learning computations, monitoring the fitness of each generation to ascertain if it reaches the target value. This approach is then compared with the computational requirements of existing methods.The learning process involves iteratively training generations to ensure that the fitness adequately converges.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.71-72
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• 2013

최근 연구 개발되고 있는 스토리지 클래스 메모리는 정체되어 있는 스토리지와 DRAM 산업에 큰 변화를 가져올 것으로 예상된다. 현재 컴퓨팅 환경에서 스토리지의 성능 저하요소가 큰 이슈로 야기되어지는 가운데 본 논문에서는 TPC-C 벤치마크를 이용하여 임의 쓰기와 덮어 쓰기 연산 시 발생되는 문제점들을 분석한다. 실험 결과를 통해 향후 스토리지 클래스 메모리를 활용하여 기존 쓰기 연산 시 발행 하는 문제점들을 해결할 수 있는 방안에 대해 논의 한다.

• Journal of KIISE:Databases
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• v.28 no.3
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• pp.494-511
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• 2001

In the environment that database management systems manage disk spaces for storing databases directly, this paper proposes a correct and efficient scheme of performing pending actions for the removal of database files. As for performing pending actions, upon performing recovery, the recovery process must identify unperformed pending actions of not-yet-terminated transactions and then perform those actions completely. Making the recovery process identify those actions through the analysis of log records in the log file is the basic idea of this paper. This scheme, as an extension of the execution of transactions, fuzzy checkpoint, and recovery of ARIES, uses the following methods: First, to identify not-yet-terminated transactions during recovery, transactions perform pending actions after writing 'pa_start'log records that signify both the commit of transactions and the start of executing pending actions, and then write 'eng'log records. Second, to restore pending-actions-lists of not-yet-terminated transactions during recovery, each transaction records its pending-actions-list in 'pa_start'log record and the checkpoint process records pending-actions-lists of transactions that are decided to be committed in 'end_chkpt'log record. Third, to identify the next pending action to perform during recovery, whenever a page is updated during the execution of pending actions, transactions record the information that identifies the next pending action to perform in the log record that has the redo information against the page.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1203-1212
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• 2013

In this paper, an intra prediction hardware architecture is proposed to reduce computational complexity of intra prediction in HEVC decoder. The architecture uses shared operation units and common operation units and adopts a fast smoothing decision algorithm and a fast algorithm to generate coefficients of a filter. The shared operation unit shares adders processing common equations to remove the computational redundancy. The unit computes an average value in DC mode for reducing the number of execution cycles in DC mode. In order to reduce operation units, the common operation unit uses one operation unit generating predicted pixels and filtered pixels in all prediction modes. In order to reduce processing time and operators, the decision algorithm uses only bit-comparators and the fast algorithm uses LUT instead of multiplication operators. The proposed architecture using four shared operation units and eight common operation units which can reduce execution cycles of intra prediction. The architecture is synthesized using TSMC 0.13um CMOS technology. The gate count and the maximum operating frequency are 40.5k and 164MHz, respectively. As the result of measuring the performance of the proposed architecture using the extracted data from HM 7.1, the execution cycle of the architecture is about 93.7% less than the previous design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8A
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• pp.1231-1237
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• 2000

DMT기반 VDSL 시스템에서 채널의 주파수 특성에 따라 각 부채널에 각기 다른 비트를 할당하는 "Bit allocation algorithm"은 DMT기반 시스템의 초기화 과정에 필수적으로 사용되며 초기화 시간을 단축하기위해 이알고리즘의 고속화가 필요하다 기존의 알고리즘인 Chow Campello가제시한 알고리즘들은 ADSL과 같이 부채널수가 적은 응용분야에서는 적용 가능했으나 부채널 수가 ADSL의 16배에 이르는 VDSL과 같은 경우에는 계산량이 과다하기 때문에 실시간 적용이 어렵다. 본 논문에서는 수신단에서 계산된 SNR을 미리 계산된 기준 SNR 값과 비교하는 방법을 이용하여 계산량을 줄인 새로운 비트 할당 알고리즘을 제시한다. 제안된 알고리즘은 기존 알고리즘에서 N.log2N의 연산이 필요한 SNR을 내림차순으로 분류하는 과정을 없앴고 log2 연산 덧셈 및 나눗셈의 연산을 단순한 비교 연산으로 대체함으로서 보다 고속으로 각 부채널에 할당할 비트 수를 계산할수 있다 그리고 제안된 고속 알고리즘을 VDSL 시스템에 적용한 결과 기존의 알고리즘인 Chow 알고리즘과 동일한 성능을 보임을 확이하였다.보임을 확이하였다.

• Journal of the Korea Society of Computer and Information
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• v.6 no.2
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• pp.27-33
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• 2001

In this thesis, we present a simple and efficient recovery method, called ARIES/SR(ARIES/Selective Redo) which is based on ARIES(Algorithm for Recovery and Isolation Exploiting Semantics) ARIES performs redo for all updates done by either nonloser transaction or loser transaction, and thus significant overhead appears during restart after a system failure. To reduce this overhead, we propose ARIES/SR recovery algorithm. In this algorithm, to reduce the redo operations, redo is performed, using log record for updates done by only nonloser transaction. Also selective undo is performed. using log record for update done by only loser transaction for reducing recovery operation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.9 no.4
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• pp.7-16
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• 1972

A prototype of photoelectric photometer has been developed by all solid state operational amplifiers. The amplification of low-level anode currents from photomultiplier tube corresponding to a given incident light intensity and logarithmic transfer for star's magnitude nleasurements are achieved by the same operational amplifier. It is important to select low input bias currents for stable performance because the resolution is primarily limited by the bias currents. As such, they offer a higher reliable and economical for a large number of electrometer amplifier applications which have traditionaly been fulfilled by vacuum electrometer tubes or vibrating reed electrometers.