• Education of Primary School Mathematics
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• v.11 no.1
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• pp.1-19
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• 2008

This study analyzed the repeated error patterns in division of fraction by elementary students through observation of their test papers. The questions for this study were following. First, what is the most changable thing among the repeated error patterns appeared in division of fraction by elementary students? Second, what is the most frequent error patterns in division of fraction by elementary students? First of all, the ratios of incorrect answers in division of fraction by general students were researched. This research was the only one time. The purpose was to know what kind of compositions in the problems were appeared more errors. Total 554 6th grade students(300 boys and 254 girls) from 6 elementary schools in Seoul are participated in this research. On the basis of this, the study for analysis began in earnest. 5 tests made progress for about 4 months. Total 181 6th grade students(92 boys and 89 girls) from S elementary school in Seoul were participated in this. After each test, to confirm the errors and to classify them were done. Then the repeated error patterns were arranged into 4 types: alpha, beta, gamma and delta type. Consequently, conclusions can be derived as follows. First, most students modify their errors as time goes by even though they make errors about already learned contents. Second, most students who appeared errors make them continually caused a reciprocal of natural number in the divisor when they calculate computations about '(fraction) $\div$ (natural number)'. Third, most students recognize that the divisor have to change the reciprocal when they calculate division of fraction through they modify their errors repeatedly.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.80-87
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• 2013

A novel instrumentation amplifier(IA) using positive polarity current-conveyor(CCII+) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of two CCII+, three resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into two CCII+ used voltage and current follower converts into same currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the CCII+ and used commercial op-amp LF356. Simulation results show that voltage follower used CCII+ has offset voltage of 0.21mV at linear range of ${\pm}$4V. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the gain of 60dB was 400kHz. The IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 130mW at supply voltage of ${\pm}$5V.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.3
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• pp.97-107
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• 2017

In the field of automatic door, the infrared rays and microwave sensor are much used as the important components in charge of the motor's operation control of open and close through the incoming signal of object recognition. In case of existing system that the sensor of the infrared rays and microwave are applied to the automatic door, there are many malfunctions by the infrared rays and visible rays of the sun. Because the automatic doors are usually installed outside of building in state of exposure. The environmental change by temperature difference occurs the noise of object recognition detection signal. With this problem, the hardware fault that the detection sensor is unable to follow the object moving rapidly within detection area makes the sensing blind spot. This fault should be improved as soon as possible. Because It influences safety of passengers who use the automatic doors. This paper conducted an experiment to improve the detection area by installing extra ultrasonic sensor besides existing detection sensor. So, this paper realize the computing circuit and detection algorithm which can correctly and rapidly process the access route of objects moving fast and the location area of fixed obstacles by applying detection and advantages of ultrasonic signal to the automatic doors. With this, It is proved that the automatic door applying ultrasonic sensor is improved detection area of blind spot sensing through field test and improvement plan is proposed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.10
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• pp.1-9
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• 2001

The MAC (Medium Access Control) protocol is needed for the OLT(Optical Line Termination) to allocate bandwidth to ONUs(Optical Network Units) and ONTs(Optical Network Terminations) dynamically in the ATM PON(Passive Optical Network). With the protocol, the OLT gathers ONUs' informations and provides grants efficiently to each ONU. Two important functions of the MAC protocol is the grant request procedure and the grant distribution algrithm. The latter has the greatest arithmetic portion in the TC(Transmission Convergence) module, occupies a relatively large portion of the overall chip area, has often been the limiting factor in terms of speed, and should be designed to guarantee the quality of service for various traffics. In this paper, we implement the MAC with the FPGA which can allocate grants dynamically according to the queue length information and the number of active ONUs and distribute grants uniformly to minimize the cell delay variation for each ONU. The structure of the MAC scheduler for the dynamic bandwidth assignment has a programmable look-up table. Also, it has a simple structure, the less chip area, and the lower delay time.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.1
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• pp.123-134
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• 2010

In this paper we propose ubiquitous virtual reality framework and its application for fostering a sustainable content ecosystem in the convergence space of virtual reality and real space. The ubiquitous virtual reality framework supports fundamental infrastructure which consists of platforms for end-users and service providers and dual space management. The platform for the service provider allows experts to generate contents related to real objects while the platform for the end-users allows to consume, share and regenerate the contents contextually augmented over real objects. The dual space management stores, visualizes and provides the contents generated and extended by them for connecting different users and service providers. The proposed framework allows users to continuously generate, share and extend the contents and thus contribute to making multimedia service environment. We also implemented and evaluated the framework consisting of a desktop authoring platform, mobile authoring platform and a dual space management server. We then introduced a promising application scenario to show how the content ecosystem is empowered by ubiquitous virtual reality framework and is realized in our life. Consequently, we are expecting that the ubiquitous virtual reality technology will play a vital role in building continuously evolving multimedia service environment for the future computing environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.37-47
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• 2011

Real picture like high quality computer graphic is widely used in various fields and shader processor, a key part of a graphic processor, has been advanced to programmable unified shader. However, The existing graphic processors have been optimized to commercial algorithms, so development of an algorithm which is not based on it requires an independent shader processor. In this paper, we have designed and implemented a control unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed control unit. Hardware resource usage rate are measured by implementing directly on FPGA Virtex-4 and execution speed are verified by applying ASIC library. the result of an evaluation shows that the control unit has the commands more about 1.5 times compared to the other shader processors that is a behavior similar to the control unit and with a number of processing units used in a shader processor, compared with the other processors, overall performance of the control unit is improved about 3.1 GFLOPS.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.87-95
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• 1996

A new design scheme for the fuzzy pattern matching classifier (FPMC) is proposed. in conventional design of FPMC, there are no exact information about the membership function of which shape and number critically affect the performance of classifier. So far, a trial and error or heuristic method is used to find membership functions for the input patterns. But each of them have limits in its application to the various types of pattern recognition problem. In this paper, a new method to find the appropriate shape and number of membership functions for the input patterns which minimize classification error is proposed using genetic algorithms(GAs). Genetic algorithms belong to a class of stochastic algorithms based on biological models of evolution. They have been applied to many function optimization problems and shown to find optimal or near optimal solutions. In this paper, GAs are used to find the appropriate shape and number of membership functions based on fitness function which is inversely proportional to classification error. The strings in GAs determine the membership functions and recognition results using these membership functions affect reproduction of next generation in GAs. The proposed design scheme is applied to the several patterns such as tire tread patterns and handwritten alphabetic characters. Experimental results show the usefulness of the proposed scheme.