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A Study on an Error Correction Code Circuit for a Level-2 Cache of an Embedded Processor (임베디드 프로세서의 L2 캐쉬를 위한 오류 정정 회로에 관한 연구)

  • Kim, Pan-Ki;Jun, Ho-Yoon;Lee, Yong-Surk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.1
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    • pp.15-23
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    • 2009
  • Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

High-Order Temporal Moving Average Filter Using Actively-Weighted Charge Sampling (능동-가중치 전하 샘플링을 이용한 고차 시간상 이동평균 필터)

  • Shin, Soo-Hwan;Cho, Yong-Ho;Jo, Sung-Hun;Yoo, Hyung-Joun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.2
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    • pp.47-55
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    • 2012
  • A discrete-time(DT) filter with high-order temporal moving average(TMA) using actively-weighted charge sampling is proposed in this paper. To obtain different weight of sampled charge, the variable transconductance OTA is used prior to charge sampler, and the ratio of charge can be effectively weighted by switching the control transistors in the OTA. As a result, high-order TMA operation can be possible by actively-weighted charge sampling. In addition, the transconductance generated by the OTA is relatively accurate and stable by using the size ratio of the control transistors. The high-order TMA filter has small size, increased voltage gain, and low parasitic effects due to the small amount of switches and sampling capacitors. It is implemented in the TSMC $0.18-{\mu}m$ CMOS process by TMA-$2^2$. The simulated voltage gain is about 16.7 dB, and P1dB and IIP3 are -32.5 dBm and -23.7 dBm, respectively. DC current consumption is about 9.7 mA.

A Study on Efficient and Secure user Authentication System based on Smart-card (효율적이고 안전한 스마트카드 기반 사용자 인증 시스템 연구)

  • Byun, Jin-Wook
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.2
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    • pp.105-115
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    • 2011
  • User authentication service is an absolutely necessary condition while securely implementing an IT service system. It allows for valid users to securely log-in the system and even to access valid resources from database. For efficiently and securely authenticating users, smart-card has been used as a popular tool because of its convenience and popularity. Furthermore the smart-card can maintain its own power for computation and storage, which makes it easier to be used in all types of authenticating environment that usually needs temporary storage and additional computation for authenticating users and server. First, in 1981, Lamport has designed an authentication service protocol based on user's smart-card. However it has been criticized in aspects of efficiency and security because it uses hash chains and the revealment of server's secret values are not considered. Over the years, many smart-card based authentication service protocol have been designed. Very recently, Xu, Zhu, Feng have suggested a provable and secure smart-card based authentication protocol. In this paper, first, we define all types of attacks in the smart-card based authentication service. According to the defined attacks, however, the protocol by Xu, Zhu, Feng is weak against an attack that an attacker with secret values of server is able to impersonate a valid user without knowing password and secret values of user. An efficient and secure countermeasure is suggested, then the security is analyzed.

Parallelization Method of Slice-based video CODEC (슬라이스 기반 비디오 코덱 병렬화 기법)

  • Nam, Jung-Hak;Ji, Bong-Il;Jo, Hyun-Ho;Sim, Dong-Gyu;Cho, Dae-Sung
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.47 no.6
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    • pp.48-56
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    • 2010
  • Recently, we need to dramatically speed up real-time video encoding and decoding on mobile devices because complexity of video CODEC is significantly increasing along with the demand for multimedia service of high-quality and high-definition videos by users. A variety of research is conducted for parallelism of video processing using newly developed multi-core platforms. In this paper, we propose a method of parallelism based on slice partition of video compression CODEC. We propose a novel concept of a parallel slice for parallelism and propose a new coding order to be adequate to the parallel slice which keeps high coding efficiency. To minimize synchronization time of multiple parallel slices, we also propose a synchronization method to determinate whether the parallel slice could be independently decoded or not. Experimental results shows that we achieved 27.5% (40.7%) speed-up by parallelism with bit-rate increase of 3.4% (2.7%) for CIF sequences (720p sequences) by implementing the proposed algorithm on the H.264/AVC.

Efficient Intermediate Joint Estimation using the UKF based on the Numerical Inverse Kinematics (수치적인 역운동학 기반 UKF를 이용한 효율적인 중간 관절 추정)

  • Seo, Yung-Ho;Lee, Jun-Sung;Lee, Chil-Woo
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.47 no.6
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    • pp.39-47
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    • 2010
  • A research of image-based articulated pose estimation has some problems such as detection of human feature, precise pose estimation, and real-time performance. In particular, various methods are currently presented for recovering many joints of human body. We propose the novel numerical inverse kinematics improved with the UKF(unscented Kalman filter) in order to estimate the human pose in real-time. An existing numerical inverse kinematics is required many iterations for solving the optimal estimation and has some problems such as the singularity of jacobian matrix and a local minima. To solve these problems, we combine the UKF as a tool for optimal state estimation with the numerical inverse kinematics. Combining the solution of the numerical inverse kinematics with the sampling based UKF provides the stability and rapid convergence to optimal estimate. In order to estimate the human pose, we extract the interesting human body using both background subtraction and skin color detection algorithm. We localize its 3D position with the camera geometry. Next, through we use the UKF based numerical inverse kinematics, we generate the intermediate joints that are not detect from the images. Proposed method complements the defect of numerical inverse kinematics such as a computational complexity and an accuracy of estimation.

Tile, Slice, and Deblocking Filter Parallelization Method in HEVC (HEVC 복호기에서의 타일, 슬라이스, 디블록킹 필터 병렬화 방법)

  • Son, Sohee;Baek, Aram;Choi, Haechul
    • Journal of Broadcast Engineering
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    • v.22 no.4
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    • pp.484-495
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    • 2017
  • The development of display devices and the increase of network transmission bandwidth bring demands for over 2K high resolution video such as panorama video, 4K ultra-high definition commercial broadcasting, and ultra-wide viewing video. To compress these image sequences with significant amount of data, High Efficiency Video Coding (HEVC) standard with the highest coding efficiency is a promising solution. HEVC, the latest video coding standard, provides high encoding efficiency using various advanced encoding tools, but it also requires significant amounts of computation complexity compared to previous coding standards. In particular, the complexity of HEVC decoding process is a imposing challenges on real-time playback of ultra-high resolution video. To accelerate the HEVC decoding process for ultra high resolution video, this paper introduces a data-level parallel video decoding method using slice and/or tile supported by HEVC. Moreover, deblocking filter process is further parallelized. The proposed method distributes independent decoding operations of each tile and/or each slice to multiple threads as well as deblocking filter operations. The experimental results show that the proposed method facilitates executions up to 2.0 times faster than the HEVC reference software for 4K videos.

Broadcast Encryption System Using Secret Sharing and Subset Difference Methods (비밀분산 기법과 Subset Difference 기법을 이용한 브로드캐스트 암호시스템)

  • Lee, Jae Hwan;Park, Jong Hwan
    • Journal of Broadcast Engineering
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    • v.20 no.1
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    • pp.92-109
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    • 2015
  • Broadcast encryption is a cryptographic primitive that allows a sender to securely broadcast a message to a set of receivers. The most influential broadcast encryption system was proposed in 2001 by Naor, Naor, Lotspiech, based on a pseudo-random generator and the Subset Difference (SD) method. In this paper, we suggest a new broadcast encryption system that is based on secret sharing and SD methods. On an efficiency aspect, our system achieves O(r) transmission cost, O($log^2n$) storage cost, and O(1) computational cost for the number n of users and the number r of revoked users. Compared to O(log n) computational cost in the previous SD method, our system has the advantage that it needs only constant-sized computational cost for decryption, regardless of the number n or r. On a security aspect, our system can achieve tighter security reduction than the previous SD method and the gap of security loss is about O(n log n). Moreover, our result shows that it is possible to give the effect of the SD method while using an information-theoretically secure key distribution technique as in the Complete Subtree method.

kNN Query Processing Algorithm based on the Encrypted Index for Hiding Data Access Patterns (데이터 접근 패턴 은닉을 지원하는 암호화 인덱스 기반 kNN 질의처리 알고리즘)

  • Kim, Hyeong-Il;Kim, Hyeong-Jin;Shin, Youngsung;Chang, Jae-woo
    • Journal of KIISE
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    • v.43 no.12
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    • pp.1437-1457
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    • 2016
  • In outsourced databases, the cloud provides an authorized user with querying services on the outsourced database. However, sensitive data, such as financial or medical records, should be encrypted before being outsourced to the cloud. Meanwhile, k-Nearest Neighbor (kNN) query is the typical query type which is widely used in many fields and the result of the kNN query is closely related to the interest and preference of the user. Therefore, studies on secure kNN query processing algorithms that preserve both the data privacy and the query privacy have been proposed. However, existing algorithms either suffer from high computation cost or leak data access patterns because retrieved index nodes and query results are disclosed. To solve these problems, in this paper we propose a new kNN query processing algorithm on the encrypted database. Our algorithm preserves both data privacy and query privacy. It also hides data access patterns while supporting efficient query processing. To achieve this, we devise an encrypted index search scheme which can perform data filtering without revealing data access patterns. Through the performance analysis, we verify that our proposed algorithm shows better performance than the existing algorithms in terms of query processing times.

Design of Partial Product Accumulator using Multi-Operand Decimal CSA and Improved Decimal CLA (다중 피연산자 십진 CSA와 개선된 십진 CLA를 이용한 부분곱 누산기 설계)

  • Lee, Yang;Park, TaeShin;Kim, Kanghee;Choi, SangBang
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.11
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    • pp.56-65
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    • 2016
  • In this paper, in order to reduce the delay and area of the partial product accumulation (PPA) of the parallel decimal multiplier, a tree architecture that composed by multi-operand decimal CSAs and improved CLA is proposed. The proposed tree using multi-operand CSAs reduces the partial product quickly. Since the input range of the recoder of CSA is limited, CSA can get the simplest logic. In addition, using the multi-operand decimal CSAs to add decimal numbers that have limited range in specific locations of the specific architecture can reduce the partial products efficiently. Also, final BCD result can be received faster by improving the logic of the decimal CLA. In order to evaluate the performance of the proposed partial product accumulation, synthesis is implemented by using Design Complier with 180 nm COMS technology library. Synthesis results show the delay of the proposed partial product accumulation is reduced by 15.6% and area is reduced by 16.2% comparing with which uses general method. Also, the total delay and area are still reduced despite the delay and area of the CLA are increased.

Parallel clustering technology for real-time LWIR band image processing (실시간 LWIR 밴드 영상 처리를 위한 병렬 클러스터링 기술)

  • Cho, Yongjin;Lee, Kyou-seung;Hong, Seongha;Oh, Jong-woo;Lee, DongHoon
    • Proceedings of the Korean Society for Agricultural Machinery Conference
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    • 2017.04a
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    • pp.158-158
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    • 2017
  • 비닐포장 하부에 위치한 콩의 생장 초기에 발생한 초엽을 인식하기 위한 연구를 수행중이다. 선행 연구에서 비닐포장에 접촉한 콩 초엽으로 인해 비닐포장 상부 표면의 열 반응 분포에 변화가 있음을 발견하였다. 현장에서 주행 중에 콩 초엽의 위치를 실시간으로 인식하고 연동된 선형 또는 회전형 엑츄에이터를 제어하여 정확한 위치에 천공을 수행하기 위해서는 계측 시스템과 제어 시스템간의 시간적 차이를 최소할 수 있는 실시간 신호 처리 기술이 필수적이다. 선행 연구에서 사용한 다중 IR 센서의 분해능은 $16{\times}4pixel$이며 주파수는 3 Hz로, 폭이 30cm 내외인 비닐포장 상부의 정밀 분석에 한계가 있음을 발견하였다. 이를 해결하기 위하여 분해능과 계측 주기를 개선할 수 있는 초소형 ($1cm{\times}1cm{\times}1cm$) 열화상 센서를 이용하였다. LWIR(Longwave infrared)영역에 해당하는 $8{\mu}m{\sim}14{\mu}m$의 영역에서 $0.05^{\circ}C$의 분해능을 보이는 $ Lepton^{TM}$ (500-0690-00, FLIR, Goleta, CA)모델을 사용하였다. 프레임당 $80{\times}60$ 픽셀의 정보가 2 Byte의 단위로 계측이 되며 9 Hz의 주파수로 대상면의 열 분포를 측정할 수 있다. 이론적으로 초당 정보 전송량은 86,400 Byte ($80{\times}60{\times}2{\times}9$)이며, 1 m를 진행하는 주행형 천공기에 적용할 경우 1 프레임당 10cm 정도의 면적을 측정하므로, 최대 위치 판정 분해능은 약 10 cm / 60 pixel = 0.17 cm/pixel로 상대적으로 정밀한 위치 판별이 가능하다. $80{\times}60{\times}2Byet$의 정보를 0.1초 이내에 분석해야 하는 기술적 과제를 해결하기 위하여 천공 작업기에 적합한 상용 SBC(Single board computer)의 클럭 속도(1 Ghz)로 처리 가능한 공간 분포 분석 알고리즘을 개발하였다. 전체 이미지 도메인을 한 번에 분석하는데 소요되는 시간을 최소화하기 위하여 공간정보 행렬을 균등히 배분하고 별도의 프로세서에서 Feature를 분석한 후 개별 프로세서의 결과를 경합식으로 판정하는 기술을 연구하였다. 오픈 소스인 MPICH(www.mpich.org) 라이브러리를 이용하여 개발한 신호 분석 프로그램을 클러스터링으로 연동된 개별 코어에 설치/수행 하였다. 2D 행렬인 열분포 정보를 공간적으로 균등 분배하여 개별 코어에서 행렬의 Spatial domain analysis를 수행하였다. $20{\times}20$의 클러스터링 단위를 이용할 경우 총 12개의 코어가 필요하였으며, 초당 10회의 연산이 가능함을 확인하였다. 병렬 클러스터링 기술을 이용하여 1m/s 내외의 주행 속도에 대응이 가능한 비닐포장 상부 열 분포 분석 시스템을 구현하였다.

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