• Convergence Security Journal
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• v.17 no.2
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• pp.15-22
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• 2017

This paper presents new 8-bit implementation of AES. Most typical 8-bit AES designs are to reduce the circuit area by sacrificing its throughput. The presented AES architecture employs two separated S-box to perform round operation and key generation in parallel. From the simulation results of the proposed AES-128, the maximum critical path delay is 13.0ns. It can be operated in 77MHz and the throughput is 15.2 Mbps. Consequently, the throughput of the proposed AES has 1.54 times higher throughput than the other counterpart although the area increasement is limited in 1.17 times. The proposed AES design enables very low-area design without sacrificing its performance. Thereby, it can be suitable for the various IoT applications that need high speed communication.

• Journal of IKEEE
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• v.25 no.1
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• pp.174-179
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• 2021

An Edwards curve cryptography (EdCC) core supporting point scalar multiplication (PSM) on Edwards curves of Edwards25519 and Edwards448 was designed. For area-efficient implementation, finite field multiplier based on word-based Montgomery multiplication algorithm was designed, and the extended twisted Edwards coordinates system was adopted to implement point operations without division operation. As a result of synthesizing the EdCC core with 100 MHz clock, it was implemented with 24,073 equivalent gates and 11 kbits RAM, and the maximum operating frequency was estimated to be 285 MHz. The evaluation results show that the EdCC core can compute 299 and 66 PSMs per second on Edwards25519 and Edwards448 curves, respectively. Compared to the ECC core with similar structure, the number of clock cycles required for 256-bit PSM was reduced by about 60%, resulting in 7.3 times improvement in computational performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.8
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• pp.1095-1102
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• 2021

A scalable ECC architecture with high scalability and flexibility between performance and hardware complexity is proposed. For architectural scalability, a modular arithmetic unit based on a one-dimensional array of processing element (PE) that performs finite field operations on 32-bit words in parallel was implemented, and the number of PEs used can be determined in the range of 1 to 8 for circuit synthesis. A scalable algorithms for word-based Montgomery multiplication and Montgomery inversion were adopted. As a result of implementing scalable ECC processor (sECCP) using 180-nm CMOS technology, it was implemented with 100 kGEs and 8.8 kbits of RAM when N_PE=1, and with 203 kGEs and 12.8 kbits of RAM when N_PE=8. The performance of sECCP with N_PE=1 and N_PE=8 was analyzed to be 110 PSMs/sec and 610 PSMs/sec, respectively, on P256R elliptic curve when operating at 100 MHz clock.

• The Journal of Information Technology
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• v.4 no.3
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• pp.155-163
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• 2001

In this paper, we implemented sigmoid active function which make it difficult to design of the digital neuron networks. Therefore, we designed of the high speed processing of the sigmoid function in order to digital neural networks. we designed of the MAC(Multiplier and Accumulator) operation unit used residue number system without carry propagation for the high speed operation. we designed of MAC operation unit and sigmoid processing unit are proved that it could run of the high speed. On the simulation, the faster than 4.6ns on the each order, we expected that it adapted to the implementation of the high speed digital neural network.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06b
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• pp.372-374
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• 2012

아날로그 회로는 가장 기본적인 전기/전자 회로로써 현재도 높은 중요도를 가지고 있지만, 설계를 위해서는 전문적인 지식이나 기술이 반드시 필요하다. 그래서, 아날로그 회로를 설계하기 위해 진화 연산을 이용한 기법이 연구되어 왔다. 진화연산은 최적화 문제를 해결하는 한 방법으로써 다양한 문제에 적용 가능하다. 하지만, 많은 경우 매우 오랜 시간이 걸려 재현이 어렵고 계산비용이 많이 요구되어왔다. 하지만, 최근 들어 진화전략을 이용하여 작은 집단 크기로 아날로그 회로를 진화시킬 수 있는 방법이 제안되었다. 본 연구에서는 진화전략을 이용한 방법에 기반하여, 내고장성을 가진 회로를 설계하는 기법을 제안하고, 실험을 통하여 기본 진화전략 알고리즘과 비교한다. 그 결과, 제안한 방법을 통해 생성한 회로는 기본 알고리즘을 사용했을 때 보다 고장으로 인해 소자의 값이 변경되었을 때 성능하락이 더 적었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.11a
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• pp.30-32
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• 2022

다가오는 양자 컴퓨터 시대에 대비하여, 양자 컴퓨터상에서의 암호 분석은 활발한 연구 분야 중 하나이다. 양자 알고리즘을 사용한 암호 분석 시, 대상 암호는 반드시 양자 회로로 구현되어 양자 컴퓨터상에서 동작될 수 있어야 한다. 이에 공개키 암호인 RSA, ECC의 핵심 연산 또는 다양한 대칭키 암호들에 대해 양자 회로로 최적화 구현하는 연구들이 발표되고 있다. AES는 고전 컴퓨터상에서 뿐만 아니라, 양자 컴퓨터상에서 활발한 최적화 구현 대상이다. AES의 양자 회로 구현 시, 가장 많은 양자 자원이 필요한 연산은 S-Box이다. 이에 본 논문에서는 다양한 AES 양자 구현에서의 다양한 S-Box 양자회로 구현에 대해 살펴보고 다양한 최적화 특징에 대해 살펴본다.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.1
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• pp.91-95
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• 2008

Flash memory is widely used in embedded systems because of its benefits such as non-volatile, shock resistant, and low power consumption. But NAND flash memory suffers from out-place-update, limited erase cycles, and page based read/write operations. To solve these problems, log-structured filesystem was proposed such as YAFFS. However, YAFFS sequentially retrieves an array of all block information to allocate free block for a write operation. Also before the write operation, YAFPS read the array of block information to find invalid block for erase. These could reduce the performance of the filesystem. This paper suggests fast operation method for NAND flash filesystem that solves the above-mentioned problems. We implemented the proposed methods in YAFFS. And we measured the performance compared with the original technique.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.3
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• pp.134-142
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• 2002

Quadtree, which is a hierarchical data structure, is a very important data structure to represent binary images. The linear quadtree representation as a way to store a quadtree is efficient to save space compared with other representations. Therefore, it has been widely studied to develop efficient algorithms to execute operations related with quadtrees. The window operation is one of important geometry operations in image processing, which extracts a sub-image indicated by a window in the image. In this paper, we present an algorithm to perform the window operation of binary images represented by quadtrees, using three-dimensional $n{\times}n{\times}n$ processors on RMESH(Reconfigurable MESH). This algorithm has constant-time complexity by using efficient basic operations to route the locational codes of quardtree on the hierarchical structure of $n{\times}n{\times}n$ RMESH.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.84-95
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• 2006

In H/W implementation for the finite field the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. In this paper, we propose a new, simpler, parallel multiplier over $GF(2^m)$ having a Gaussian normal basis of type k, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{mk})$ containing a type-I optimal normal basis. For k=2,4,6 the time and area complexity of the proposed multiplier is the same as tha of the best known Reyhani-Masoleh and Hasan multiplier.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.44-59
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• 2006

This paper describes the efficient implementation of DNA sequence generate system with genetic algorithm for reducing computation time of NACST. The proposed processor is based on genetic algerian with fitness functions which would suit the point of reference for generated sequences. In order to implement efficient hardware structure, we used the pipelined structure. In addition our design was applied the parallelism to achieve even better simulation time than the sequence generator system which is designed on software. In this paper, our hardware is implemented on the FPGA board with xc2v6000 devices. Through experiment, the proposed hardware achieves 467 times speed-up over software on a PC and sequence generate performance of hardware is same with software.