• Composites Research
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• v.25 no.6
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• pp.224-229
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• 2012

The structural performance is degraded in case of embedding the array antenna for reconnaissance and surveillance into the wing skin structures. In this paper, the optimal design for the thickness of composite hat-shaped stiffener which is reinforced embedded array antenna on the simplified composite wing box was conducted. To select the basic shape of hat-shaped stiffener, structural analysis was carry out using the commercial finite element analysis program while changing the web slope and flange length of hat-shaped stiffener. The optimal thickness of the composite hat-shaped stiffeners was determined by using commercial optimization program such as VisualDOC and commercial FEA program with considering stresses and buckling constraints.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.11
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• pp.1063-1070
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• 1991

A microstrip array antenna are designed to depend on the size of rectangular microstrip patch for the relative current destribution to be 1:2:2:1 or 1:1:2:2:1:1 using Tchebyscheff polynominals, and it consist of sharp beam pattern. Gain difference between the main lobe and sidelobe is calculated for theoritical values of 21.97 db or 29.54 db. The designed microstrip array antenna are measureed various characteristics, such as return loss, resonant frequency, radiation pattern, bandwidth, beamwidth, and agreed with each other and theoretical value. Also it is presented a process of phase variation of patch array antenna depend on relative current distribution for beam scanning.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1057-1066
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• 2001

This paper describes a design for linear polarization antenna using the EMCD (electromagnetically coupled dipole). The analysis and the design of model antennas are conducted by FDTD method. Vertical and horizontal linear polarizations are easily obtained by variation of dipole position. In 1-element antenna design, mutual coupling between microstrip feed line and radiator is considered. Design parameters of each 1-element antenna with vertical and horizontal polarization are used for array design. Radiation power and main beam tilting angle can be controlled by the offset and the distance between radiating elements in an array, respectively. 5-element array antennas are fabricated and measured to prove the design validity. The results of FDTD simulation and measurement show the reasonable agreement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.702-708
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• 2000

In this paper, we designed one-dimensional VLSI array with optimal pipeline period for high speed processing fractal image compression. The algorithm is derived which is suitable for VLSI array from axed block partition algorithm. Also the algorithm satisfies high quality of image and high compression-ratio. The designed VLSI array has optimal pipeline relied because the required processing time of PEs is distributed as same as possible. As this result, we can improve the processing speed up to about 3 times. The number of input/output pins can be reduced by sharing the input/output and arithmetic unit of the domain blocks and the range blocks.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.809-812
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• 2002

본 논문은 RSA 암호시스템에서 고속 모듈러 곱셈을 위한 최적화된 시스톨릭 어레이의 설계를 제안한다. 제안된 방법에서는 미리 계산된 가산결과를 사용하여 개선된 몽고메리 모듈러 곱셈 알고리듬을 제안하고, 고속 모듈러 곱셈을 위한 새로운 구조의 시스톨릭 어레이를 설계한다. 미리 계산된 가산결과를 얻기 위해 CLA(Carry Look-ahead Adder)를 사용하였으며, 이 가산기는 덧셈연산에 있어서 캐리전달 지연이 제거되므로 연산 속도를 향상 시킬 수 있다. 제안된 시스톨릭 구조는VHDL(VHSlC Hardware Description Language)을 사용하여 동작적 수준을 기술하였고, Ultra 10 Workstation 상에서 $Synopsys^{TM}$ 툴을 사용하여 합성 및 시뮬레이션을 수행하였다. 또한, FPGA 구현을 위하여 Altera MaxplusII를 사용하여 타이밍 시뮬레이션을 수행하였고, 실험을 통하여 제안한 방법을 효율성을 확인하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.9 no.1
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• pp.135-146
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• 1999

Most public key cryptosystems are constructed based on a modular exponentiation, which is further decomposed into a series of modular multiplications. We design a new systolic array multiplier to speed up modular multiplication using Montgomery algorithm. This multiplier with simple circuit for each processing element will save about 14% logic gates of hardware and 20% execution time compared with previous one.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• The Journal of the Acoustical Society of Korea
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• v.28 no.3
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• pp.260-267
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• 2009

It is very difficult to form a desired complex sound field at a designated region precisely as an application of acoustic arrays, which is one of important objects of array systems. To solve the problem, a filter design method was suggested, which employed the concept of an inverse method using the acoustical holography based on the boundary element method. In the acoustical holography used for the source identification, the measured field data are employed to reconstruct the vibro-acoustic parameters on the source surface. In the analogous problem of source array design, the desired field data at some specific points in the sound field was set as constraints and the volume velocity at the surface points of the source plane became the source signal to satisfy the desired sound field. In the filter design, the constraints for the desired sound field are set, first. The array source and given space are modelled by the boundary elements. Then, the desired source parameters are inversely calculated in a way similar to the holographic source identification method. As a test example, a target field comprised of a quiet region and a plane wave propagation region was simultaneously realized by using the array with 16 loudspeakers.

• Electrical & Electronic Materials
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• v.6 no.1
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• pp.28-33
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• 1993

Short channel 비휘발성 SNOSFET EEPROM 기억소자를 CMOS 1 Mbit 설계규칙에 따라 제작하고 특성과 응용을 조사하였다. 논리 어레이를 실현하기 위한 SNOSFET는 4단자와 2단자 비휘발성 메모리 셀로 구성하고 이에 대한 기록과 소거 특성을 조사하였다. 결과적으로 4단자 소자와 2단자 소자의 메모리 윈도우는 각각 기록과 소거에 의하여 "1"상태와 "0"상태로 동작되는 저전도 상태와 거전도 상태를 나타냈다. 4단자 2 x 2 메트릭스 어레이는 양극성으로 동작하였으며 2단자 2 x 2 메트릭스 어레이는 단극성으로 동작하였다.릭스 어레이는 단극성으로 동작하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.4
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• pp.403-410
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• 2005

This Paper Presents development of solar may shunt switching unit with a fully regulated Power regulation for Geostationary Earth Orbit(GEO) satellite. This shunt switching unit comprises the solar may shunt modules that regulate the solar array power. These solar array shunt modules connect/disconnect the solar array segments to/from the bus through switching actions. And that is also possible simply extension to an existing design by FPGA control logic changing. In order to verify the proposed design, the control logic and worst case analysis are analyzed and the simulation and experimental results we shown.