• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1747-1754
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• 1997

The helical array antenna is designed for domestic DBS(Directcast Satellite) reception. The antenna diameter is determined 30cm with 168 element s to cover from Moojoo (beam center) to Seoul. The helical antenna with 2-turns and 4.deg. pitch angle is chosen as array elements for good axial ratio and antenna height. In array antenna design, row distance is 0.787.lambda., array distance is 0.824.lambda. in the same row. The feed is constructed using the radial waveguide to decrease the height of antenna. The measured values of the designed antenna are not only satisfied with the design goals but also similar to theoritical values except the axial ratio.

• The Transactions of the Korea Information Processing Society
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• v.6 no.12
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• pp.3662-3674
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• 1999

This paper addresses some design issues for establishing the optimal number of spare units in array systems manufactured using fault-tolerant multichip modules(MCM's) for massively parallel computing(MPC). We propose a new quantitative approach to an optimal cost-effective MCM system design under yield and reliability constraints. In the proposed approach, we analyze the effect of residual redundancy on operational reliability of fault-tolerant MCM's. In particular, the issues of imperfect support circuitry, chip assembly yield and array topology are investigated. Extensive parametric results for the analysis are provided to show that our scheme can be applied to design ways using MCM's for MPC applications more efficiently, subject to yield and reliability constraints.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.325-328
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• 2004

본 논문은 다목적실용위성 2호기의 개발에 사용한 태양전지 어레이의 설계결과를 요약하였다. 최적의 태양전지 어레이의 개발을 위하여 고효율의 갈륨-아세나이드 태양전지를 사용하였다. 태양전지를 장착하기 위한 패널은 알루미늄 허니컴이 적용되는 샌드위치 구조에 섬유강화 복합재료를 면재로 사용하였다. 다목적실용위성 2호기의 임무말기 태양전지 어레이는 최소 1,073 watts 이상의 전력을 위성부하와 탑재체에 충분히 공급할 수 있도록 개발하고 있다.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.288-291
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• 2003

본 논문에서는 모듈성과 확장성을 갖는 시스톨릭 어레이를 이용한 두 띠 행렬의 비트 연속 승산기 구현에 대하여 기술한다. 띠 폭이 3인 4$\times$4 띠 행렬이 주어질 때 워드 레블 승산기 설계를 위한 3차원 DG로부터 2차원 시스톨릭 어레이를 유도한 후, 워드 레블 PE를 비트 연속 승산기와 가산기를 이용하여 비트 레블 PE로 변환시켜 띠 행렬의 비트 레블 승산기를 설계한다. 구현된 워드 레블 승산기와 비트 레블 승산기는 RT 수준에서 VHDL로 모델링하여 동작을 검증하였다. 검증된 시스톨릭 어레이를 이용한 워드 레블 승산기와 비트 레블 승산기는 Hynix에서 제공하는 0.35$\mu\textrm{m}$ 셀 라이브러리를 사용하여 Synopsys design compiler로 합성되었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.11a
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• pp.24-26
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• 2022

시스톨릭 어레이는 DNN training 등 인공지능 연산의 대부분을 차지하는 행렬 곱셈을 수행하기 위한 하드웨어 구조로 많이 사용되지만, sparsity 가 높은 행렬을 연산할 때 불필요한 동작으로 인해 효율성이 크게 떨어진다. 본 논문에서 제안된 유동적 시스톨릭 어레이는 matrix condensing, weight switching, 그리고 direct output path 의 방법과 구조를 통해 sparsity 가 높은 행렬 곱셈의 수행 사이클을 줄일 수 있다. 시뮬레이션을 통해 기존 시스톨릭 어레이와 유동적 시스톨릭 어레이의 성능을 비교하였으며 8×8, 16×16, 32×32 의 크기를 가진 행렬을 동일 크기의 시스톨릭 어레이로 연산하였을 때 필요 사이클 수를 최대 12 사이클 절감할 수 있는 것을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.5
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• pp.34-42
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• 2002

In this paper, we designed the VLSI array architecture for the high speed processing of the motion estimation used by block matching algorithm. We derived the one dimensional systolic array from the full search block matching algorithm. The data and control signals of the proposed systolic array are passed through adjacent processing element. So proposed architecture has temporal and spatial locality. The I/O ports exists only in the first and last processing elements of the array. This architecture has low pin counts and modular expandability. So the proposed array architecture can be cascaded for different block size and search range.

• Aerospace Engineering and Technology
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• v.12 no.2
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• pp.140-146
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• 2013

In this study, we discuss about the printed reflectarray antenna design for parabolic reflector volume reduction. For this, we simulated and measured the phase characteristics of the unit array element of reflectarray antenna using waveguide simulator. As a results, the maximum phase variation is $298^{\circ}$ by simulation, the average phase variation is $309^{\circ}$ by measurement in 10GHz. And the printed Reflectarray antenna gain is 28.3dBi, 3dB beamwidth is E-plane $5.1^{\circ}$, H-plane $5.2^{\circ}$, sidelobe level is E-plane -11.4dB, H-plane -17.6dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.40-48
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• 2013

This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.969-973
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• 1995

In this paper, a new parallel Multiplier array is proposed to reduce the multiplication time by modifying CAS(carry select adder) cell structure used in the conventional parallel multiplier array. It is named MCSA(modified CSA) that assignes the addend and augend to the inputs of CSA faster than Ci(carry input). Also the designed DCSA (doubled inverted input CSA) is appended after the last product term for the carry propagation adder. The proposed scheme is designed with MCSA and DCSA, and simulated. It is verified that the circuit size is increased about 13% compared with the conventional multiplier array with CSA cell but the operation time is reduced about 52%.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.3
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• pp.9-15
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• 2011

The microstrip reflectarray antenna is rapidly becoming an attractive alternative solution to the traditional parabolic reflector antenna. However, the bandwidth of the microstrip reflectarray using the single layer structure is very narrow. To obtain wide bandwidth characteristic, the microstrip reflectarray using the multi-layer structure has been used, but it has some disadvantages such as high cost and complicated design. In this paper, to obtain low cost and wide bandwidth, the microstrip reflectarray antenna composed of square patch with two U-slots using the single-layer structure is proposed. The proposed antenna demonstrate radiation efficiency closed to 55.5 % and 1 dB gain bandwidth over 14 % at 12.5 GHz.