• Journal of the Korean Vacuum Society
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• v.16 no.6
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• pp.414-423
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• 2007

Field Emission Display(FED) has significant advantages over existing display technologies, particularly in the area of small and high quality display. In order to test the feasibility of fabricating the System-on-Chip(SOC) with FED, we conducted the experiment to use the p-n junction as an electron beam source for the flat panel display. A novel structure was constructed to form p-n junctions by generating inversion layer with the electric field from the cantilever style gate. When we applied more than 220V at the cantilever style gate which has a height of $1{\mu}m$, avalanche breakdown onset was successfully achieved. The characteristics was compared with the electron emission from the ultra shallow junction in the avalanche region. The experiment result and the future direction were discussed.

• Journal of the Korean Vacuum Society
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• v.18 no.2
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• pp.116-126
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• 2009

It is becoming more difficult to improve the device operating speed by shrinking the size of semiconductor devices. Therefore, for a new leap forward in the semiconductor industry, the advent of silicon opto-electronic devices, i.e., silicon photonics is more desperate. Silicon Avalanche LED is one of the prospective candidates to realize the practical silicon opto-electronic devices due to its simplicity of fabrication, repeatability, stability, high speed operation, and compatibility with silicon IC processing. We conducted the measurement of the electrical characteristics and the observation of the light-emitting phenomena using optical microscopy. We analyzed the influence of the design elements such as the shape of the light-emitting area and the depth of the $n^{+}-p^{+}$ junction with simple device modeling and simulation. We compared the results of simulation and the measurement and explained the discrepancy between the results of the simulation and the measurement, and the suggestions for the improvement were given.

• ETRI Journal
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• v.8 no.4
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• pp.103-109
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• 1986

LDD(Lightly Doped Drain) 방식에 의한 MOSFET의 제조 공정 및 특성에 관하여 실험 분석하였다. MOS 소자의 채널 길이가 짧아짐에 따라 드레인 가장자리에서 자체 형성되는 높은 전계로 말미암아 애벌런치 항복 전압(avalanche breakdown voltage)이 상당히 감소 한다. 이 전압을 높여 주기 위한 기술로서 LDD 방식이 적용되었으며 종래의 제조방식에 의한 MOSFET와 비교 기술되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.1-5
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• 2011

In this paper, we optimize the gate field plate structure to improve breakdown characteristics of AlGaN/GaN HEMT by two-dimensional device simulator. We have simulated using three parameters such as field-plate length, types of insulator, and insulator thickness and thereby we checked change of the electric field distribution and breakdown voltage characteristics. As optimizing field-plate structure, electric fields concentrated near the gate edge and field-plate edge are effectively dispersed. Therefore, avalanche effect is decresed, so breakdown voltage characteristic is increased. As a result breakdown characteristics of optimized gate field-plate structure are increased by about 300% compared to those of the standard structure.

• Korean Journal of Optics and Photonics
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• v.24 no.4
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• pp.176-183
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• 2013

In this paper, we report the design, fabrication and characterization of the 3-Dimensional optical receiver for a Laser Detection And Ranging (LADAR) system. The optical receiver is composed of three parts; $16{\pm}16$ Geiger Mode InGaAs Avalanche Photodiode (APD) array device operated at 1560 nm wavelength, Read Out Integrated Circuit (ROIC) measuring the Time-Of-Flight (TOF) of the return signal reflected from target objects, a package and cooler maintaining the proper operational condition of the detector and control electronics. We can confirm that the LADAR system can detect the signal from a target up to 1.2 km away, and it showed low Dark Count Rate (DCR) of less than 140 kHz, and higher than 28%-Photon Detection Efficiency (PDE). This is considered to be the best performance of the $16{\pm}16$ FPA APD optical receiver for a LADAR system.