• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12B
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• pp.1758-1765
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• 2010

This paper proposes an architecture exploration methodology for the design of embedded cores exploiting design hierarchy. The proposed method performs systematic architecture exploration by taking different approaches for verifying designs and estimating performances depending on the hierarchy level in design process. Performance estimation tools generate profile having performance data related with design modules of an embedded core. Profile analyzer performs data-mining to acquire association rules between the design modules and performance parameters. Inference engine in the profile analyzer updates the association rules which will be used to improve the design performance at next exploration steps. To show the efficiency of the proposed architecture explorations methodology, experiments had been performed for JPEG encoder, Chen-DCT, and FFT application functions. The embedded cores designed by taking the proposed method show performance improvement by 60.8% in terms of clock cycles on the average when compared with the initial embedded core in MIPS R3000.

• Journal of Information Management
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• v.36 no.1
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• pp.103-124
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• 2005

This paper investigates knowledge management architecture which is related to the efficient storage, search, and retrieval of knowledge. It is important considerations that should be taken account in any knowledge management system. This study reviews literature and practices of the theory of current status of knowledge management architecture (KMA). Based on the review of the current practice, the characteristics and emphasis of the KMA applications are identified. It tries to suggest how the KMA should facilitate for effective and desirable directions of the KMA.

• Journal of Technology Innovation
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• v.24 no.2
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• pp.21-56
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• 2016

Despite many previous studies on catch-up, understanding on the effect of product architecture developed by latecomers on the catch-up performance remains limited. On the other hands, in contrast to the semiconductor, ship building, and automotive industry, even if Korean industry and government have invested the development of numerical controllers for machine tools in the past four decades, the industry and government have failed to achieve catch-up. Therefore, we newly examine the effect of product architecture on the catch-up performance of the Korea by implementing comparative research with periods on the evolution of product architecture of Fanuc's numerical controllers, which have achieved the largest market share in the world. We found that Fanuc developed open modular architecture based numerical controllers and provided product with customization of user requirements as well as cost effectiveness. Consequently, Fanuc has sustained market leader position since the mid-1980s. However, despite all the efforts of the industry and government, we found that the Korea failed to develop open modular architecture based numerical controllers and could not achieve significant catch-up performance. Our findings provide important theoretical backgrounds for examining the catch-up performance as well as investigating the reason why latecomers failed to achieve market catch-up even if they accomplished technological catch-up.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.12
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• pp.5072-5082
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• 2010

The Paper describes the methodology for Software Architecture Design. The key idea is to find the interfaces between the actors, modules, and communicating entities, and use them to identify the software design elements. The identified interfaces and modules are further used to find new modules and interfaces until the every design elements are found and located in the software architecture. This method starts the architecture design with finding the interfaces and enables the natural design procedure by relating the cause and results of the design. It also makes use of not only 5 architectural views for analysis and design of the software, but also concept of architecture patterns in design procedure. Especially, this method is also useful for the novice of the software architecture design.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.339-349
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• 2017

This paper proposes a four-stage algorithm for detecting lanes on a driving car. In the first stage, it extracts region of interests in an image. In the second stage, it employs a median filter to remove noise. In the third stage, a binary algorithm is used to classify two classes of backgrond and foreground of an input image. Finally, an image erosion algorithm is utilized to obtain clear lanes by removing noises and edges remained after the binary process. However, the proposed lane detection algorithm requires high computational time. To address this issue, this paper presents a parallel implementation of a real-time line detection algorithm on a multi-core architecture. In addition, we implement and simulate 8 different processing element (PE) architectures to select an optimal PE architecture for the target application. Experimental results indicate that 40×40 PE architecture show the best performance, energy efficiency and area efficiency.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2008.10a
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• pp.24-36
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• 2008

Architecture-based competition has become a very important issue in many industries. As companies seek lower cost, fast development, and more customizability at the same time, modular architecture of products and processes seem to be an inevitable choice. Existing literature, however, has only focused on the basic contents of architecture-based competition. Different competitive environments and technological competencies of incumbent companies influence the evolutionary dynamics of dominant architecture of industries. In this paper we suggest a new theoretical framework to deal with the complex co-adaptation process of architecture-based competition. We first explore the emerging modular architecture in Chinese commercial vehicle industry, and then compare it with the architecture strategies of Korean companies. Based on the explorative case study, we propose new hypotheses relating the market demand, technological competencies of major players and dominant architecture in an indus-try.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.1076-1087
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• 2010

Together with a new advent of embedded processor developed to support specific application area and it evolution, a new research of software development to support the embedded processor and its commercial challenge has been revitalized. Retargetability is typically achieved by providing target machine information, ADL, as input. The ADLs are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, assembler, profiler, and debugger. The EXPRESSION ADL follows a mixed level approach-it can capture both the structure and behavior supporting a natural specification of the programmable architectures consisting of processor cores, coprocessors, and memories. And it was originally designed to capture processor/memory architectures and generate software toolkit to enable compiler-in-the-loop exploration of SoC architecture. In this paper, we designed the class-based ADL based on the EXPRESSION ADL to promote the write-ability, extensibility and verified the validation of grammar. For this works, we defined 6 core classes and generated the EXPRESSION's compiler and simulator through the MIPS R4000 description.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10C
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• pp.1000-1010
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• 2006

This paper proposes a new architecture for DCT-based motion estimation and compensation. Previous methods do riot take sufficient advantage of the sparseness of 2-D DCT coefficients to reduce execution time. We first derive a recursion equation to perform DCT domain motion estimation more efficiently; we then use it to develop a wavefront array processor (WAP) consisting of processing elements. In addition, we show that the recursion equation enables motion predicted images with different frequency bands, for example, from the images with low frequency components to the images with low and high frequency components. The wavefront way Processor can reconfigure to different motion estimation algorithms, such as logarithmic search and three step search, without architectural modifications. These properties can be effectively used to reduce the energy required for video encoding and decoding. The proposed WAP architecture achieves a significant reduction in computational complexity and processing time. It is also shown that the motion estimation algorithm in the transform domain using SAD (Sum of Absolute Differences) matching criterion maximizes PSNR and the compression ratio for the practical video coding applications when compared to tile motion estimation algorithm in the spatial domain using either SAD or SSD.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.78-85
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• 2008

This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the poject with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.