• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.34-39
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• 2007

Serial links via backplane channels suffer from severe signal integrity problems which are normally caused by channel imperfections, such as flat loss, frequency-dependent loss, reflection, etc. Particularly, the frequency-dependent loss causes ISI(Inter-Symbol-Interference) at signal waveforms. Therefore, adaptive equalizing techniques have been exploited in many products to facilitate the ISI problem. In this paper, we present an analog adaptive equalizer circuit designed in a $0.18{\mu}m$ CMOS process. It achieves 10Gb/s data transmission through a long 34-inch backplane channel(or transmission line). The post-layout simulations demonstrate $8ps_{p-p}$ jitter with 10mW power dissipation. The core of the adaptive equalizer occupies the area of $0.56mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.71-79
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• 2013

This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver adapts to channel and chip process variation by adaptation circuit using sampler and serializer. The adaptation principle is explained. It describes technique receiving ground referenced differential signal of voltage-mode transmitter for low-power. The CTLE(Continuous Time Linear Equalizer) having 17.6 dB peaking gain to remove long tail ISI caused channel with -21 dB attenuation. The voltage margin is 210 mV and the timing margin is 0.75 UI in eye diagram. The receiver consumes 0.87 mW/Gb/s low power in 45 nm CMOS technology.

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.27-34
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• 2002

There is much interest on information communications owing to the rapid development of network and IT(Information Technology). Analog signals are converted into digital signals for information communications. However, it is very difficult to completely erase the distortion induced during the conversion of analog signals such as voices and images into digital signals. Existing audio graphic equalizer requires very complex processes to calculate the gain and coefficients of the higher-order filter which is required to generate natural sound and to satisfy the need of each person. Unfortunately it is uneconomical and very difficult to embed the existing digital audio equalizer in the system because of the complexity of the existing digital audio equalizer for high quality sound. This paper discusses the design of a new digital audio graphic equalizer(DAGEQ) which can improve system performance and the quality of audio sound, and can be embedded in the system. This new DAGEQ is designed so that the gain can be controlled automatically. The automatic control of coefficients and gain empowers real time processing and the improvement of audio quality.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.4
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• pp.779-784
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• 2020

In this paper, we improved the high frequency noise characteristics of the previously proposed hearing aid circuits for presbycusis, and we designed and fabricated a stereo hearing aid module. The cause of high frequency noise, which occurs in some cases in the previous circuits under high gain conditions, was analyzed through simulations. Two mute switches were added to adjust each boosting gain for right and left ears more accurately by muting the sound of the other ear when adjusting the gain of one ear in the stereo hearing aid module.