• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.448-451
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• 2011

SoC에서 칩 내부의 온도를 측정하기 위한 proportional-to-absolute-temperature (PTAT) 회로와 sensing 된 아날로그 신호를 디지털로 변환하기 위해 4-bit analog-to-digital converter (ADC)로 구성된 temperature sensor를 제안한다. CMOS 공정에서 vertical PNP 구조를 이용하여 PTAT 회로가 설계되었다. 온도변화에 둔감한 ADC를 구현하기 위해 아날로그 회로를 최소로 사용하는 successive approximation (SA) ADC가 이용되었다. 4-bit SA ADC는 capacitor DAC와 time-domain 비교기를 이용함으로 전력소모를 최소화하였다. 제안된 temperature sensor는 2.5V $0.25{\mu}m$ 1-poly 9-metal CMOS 공정을 이용하여 설계되었고, $50{\sim}150^{\circ}C$ 온도 범위에서 동작한다. Temperature sensor의 면적과 전력 소모는 각각 $130{\times}390\;um^2$과 868 uW이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.28-36
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• 2008

This paper describes a low-power CMOS analog front-end block for UHF band RFID tag chips. It satisfies ISO/IEC 18000-6C and includes a memory block for test. For reducing power consumption, it operates with an internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator can more exactly demodulate than conventional demodulator with low current consumption. It is designed using a $0.18{\mu}m$ CMOS technology. Measurement results show that it can operate properly with an input as low as $0.25V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.130-136
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• 2008

This paper describes a low-power high-performance analog front-end block for $UHF(860{\sim}960MHz)$ band RFID tag chips. It satisfies ISO/IEC 18000-6 type C(EPCgolbal class1. generation2.) and includes a memory block for test. For reducing power consumption, it operates with a internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator has an error rate as low as 0.014%. It is designed using a 0.18um CMOS technology. The simulation results show that the designed circuit can operate properly with an input as low as $0.2V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.875-877
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• 2011

This paper introduces a touch screen panel driver using modified charge pump circuit. The touch screen panel driver is composed of an analog circuit part which senses a touch and a digital circuit which analyse the sensed signal. To verify the functions the touch screen panel driver, a mixed-mode circuit was built and simulated using Cadence Spectre. The digital circuits were modeled with Verilog-A in order to interface with the analog circuits and verify the functionalities of the driver with less simulation time. From the simulation results, we can verify the reliable operations of the simple structured touch screen panel driver which does not include an ADC.

• Information and Communications Magazine
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• v.28 no.11
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• pp.9-15
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• 2011

CMOS 집적회로기술의 발달로 인해 디지털회로는 속도향상 소모전력 감소로 성능이 매우 많이 향상되었지만, Analog/RF 회로는 동작전압감소, 공정변화심화 등으로 인해 심각한 성능저하가 나타나고 있다. 이에 기존의 전하펌프 기반 아날로그 PLL에 대한 대안으로 All Digital PLL(ADPLL)이 개발되고 이미 상용제품에 적용되고 있다. 하지만 그 성능은 데이터변환 회로인 TDC와 DCO의 제한된 해상도로 인해 개선이 많이 필요하다. 이 두 회로는 ADPLL의 성능에 가장 큰 영향을 미치므로 본 논문에서는 지금까지 발표된 TDC와 DCO 구현사례를 중심으로 ADPLL의 연구개발동향을 살펴보고자 한다.

• Information Display
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• v.5 no.1
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• pp.13-18
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• 2004

• Information Display
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• v.6 no.5
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• pp.17-23
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• 2005

• The Magazine of the IEIE
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• v.40 no.6
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• pp.46-52
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• 2013

• Proceedings of the KIEE Conference
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• 1982.07a
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• pp.133-134
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• 1982

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.