• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.47-54
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• 2004

The growth of computer resource and network speed has increased requests for the use of remotely located computer systems by connecting through computer networks. This phenomenon has hoisted research activities for application service provision that uses server-based remote computing paradigm. The server-based remote computing paradigm has been developed as the ASP (Application Service Provision) model, which provides remote users through application sharing protocol to application programs. Security requirement such as confidentiality, availability, integrity should be satisfied to provide ASP service using centralized computing system. Existing Telnet or FTP service for a remote computing systems have satisfied security requirement by a simple access control to files and/or data. But windows-based centralized computing system is vulnerable to confidentiality, availability, integrity where many users use the same application program installed in the same computer. In other words, the computing system needs detailed security level for each user different from others, such that only authorized user or group of users can run some specific functional commands for the program. In this paper, we propose windows based centralized computing system that sets security policies for each user for the use of instructions of the application programs, and performs access control to the instructions based on the security policies. The system monitors all user messages which are executed through graphical user interface by the users connecting to the system. Ail Instructions, i.e. messages, for the application program are now passed to authorization process that decides if an Instruction is delivered to the application program based on the pre-defined security polices. This system can be used as security clearance for each user for the shared computing resource as well as shared application programs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10b
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• pp.49-53
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• 2006

본 논문에서는 복잡한 배경을 가진 영상에서 손 영역을 안정적으로 검출, 손 형상을 인식하여 그림 맞추기 응용 프로그램을 제어하는 시스템에 대해 기술한다. 피부색의 컬러 정보를 이용하여 손 영역만을 추출한 후 핑거 팁 템플릿매칭을 사용하여 손가락 끝점을 찾아낸다. 또한 손 영역의 에지 방향성 히스토그램을 구하여 얻어진 정보를 바탕으로 주성분 분석법을 사용하여 손 형상을 인식한다. 최종적으로 인식된 손 형상 정보와 손가락 끝점 추적을 이용한 명령어 실행으로 그림 맞추기 응용 프로그램을 제어 한다. 본 논문에서 제안한 알고리즘으로 그림 맞추기 응용 프로그램 제어에 적용한 결과 안정적인 실험 결과를 얻을 수 있었고, HCI 분야에서 다양하게 활용될 수 있음을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.23-30
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• 2006

This paper presents design andd verification of a circuit that improves the control-operation problems of Stored Program Optical Computer (SPOC), which is an optical computer using $LiNbO_3$ optical switching element. Since the memory of SPOC takes the Delay Line Memory (DLM) architecture and instructions that are needless of operands should go though memory access stages, SPOC memory have problems; it takes immoderate access time and unnecessary operations are executed in Arithmetic Logical Unit (ALU) because desired operations can't be selectively executed. In this paper, improvement on circuit has been achieved by removing the memory access of instructions that are needless of operands by decoding instructions before locating operand. Unnecessary operations have been reduced by sending operands to some specific operational units, not to all the operational units in ALD. We show that total execution time of a program is minimized by using the Dual Instruction Register(DIR) architecture.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.461-469
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• 2000

In the paper, the design and the implementation of the netscape plug-in and the speech synthesis enginegenerating the speech sounds from the text information of the web pages are described. The steps of the generating speech sound from an web pages are the speech synthesis plug-in is activated when the netscape finds the audio/xesp MIME data type embedded in the browsed web page; the HTML file referenced in the EMBED MTML tag is down loaded from the referenced URL to send to the commander object located in the said plug-in; The speech synthesis engine control tags and the text characters are extracted from the down loaded HTML document by the commander object the synthesized speech sounds are generated by the speech synthesis engine. The speech synthesis engine interprets the command streams from the commander objects to call the member functions for the processing of the speech segment data in the data banks. The commander object and the speech synthesis engine are designed as an independent object to enhancethe flexitility and the portability.

• Proceedings of the Korean Society of Computer Information Conference
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• 2020.01a
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• pp.77-78
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• 2020

본 논문에서는 미디어 플레이어 제어가 어려운 지체 장애인들을 위해 음성과 동작 인식 기반의 미디어 제어 애플리케이션을 설계하고 구현한다. 이 애플리케이션은 사용자의 음성 인식을 위해 먼저 명령어를 정하고, 명령에 매핑되는 키워드 관리하는 데이터 모델을 생성한다. 그리고 이 데이터 모델을 JSON 파일로 정제하여 사용한다. 그리고 키넥트 센서를 활용한 동작 인식은 오른쪽 어깨를 중심으로 오른쪽 손목의 좌표값을 인식함으로써 동작 인식 제어 컨트롤을 실행한다. 오른쪽 어깨를 기준점으로 오른쪽 손목의 좌표값으로 현재 팔의 위치를 정하고, 영역 1~4 에 따라 동작을 인식한다.

• Proceedings of the Korea Contents Association Conference
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• 2006.11a
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• pp.801-805
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• 2006

In this paper, we describe a system of controlling the pictorial puzzle program using information of hand shape. We extract hand region using skin color information and then principal component analysis uses centroidal profile information which comes blob of 2D appearance for hand shape recognition. This method suit hand shape recognition in real time because it extracts hand region accurately, has little computation quantity, and is less sensitive to lighting change using skin color information in complicated background. Finally, we controlled a pictorial puzzle with using recognized hand shape information. This method has good result when we make an experiment on application of pictorial puzzle. Besides, it can use so many HCI field.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.59-70
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• 2004

SMT(Simultaneous Multi Threading) architecture uses TLP(Thread Level Parallelism) and increases processor throughput, such that issue slots can be filled with instructions from multiple independent threads. Having multiple ready threads reduces the probability that a functional unit is left idle, which increases processor efficiency. To utilize those advantages for the SMT processors, the issue unit must control the flow of instructions from different threads and not create conflicts among those instructions, which make the SMT issue logic extremely complex. Therefore, our SMT architecture, which is modeled in this paper, uses an in-order-issue and completion scheme, and therefore, can use a simple issue mechanism with a scoreboard already instead of using register renaming or a reorder buffer. However, an SMT scoreboarding mechanism is still more complex and costlier than that of a single threaded conventional processor. This paper proposes an optimal implementation of a scoreboarding mechanism for an ARM-based SMT architecture.

• Journal of KIISE:Software and Applications
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• v.35 no.7
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• pp.452-461
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• 2008

Binary diffing is a method to find differences in similar binary executables such as two different versions of security patches. Previous diffing methods using flow information can detect control flow changes, but they cannot track constant value changes. Biffing methods using assembly instructions can detect constant value changes, but they give false positives which are due to compiling methods such as instruction reordering. We present a binary diffing method and its implementation named SCV which utilizes both structure and value information. SCV summarizes structure and constant value information from disassembled code, and matches the summaries to find differences. By analyzing a Microsoft Windows security patches, we showed that SCV found necessary differences caused by constant value changes which the state-of-the-art binary diffing tool BinDiff failed to find.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.