• Journal of KIISE:Computer Systems and Theory
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• v.31 no.5_6
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• pp.268-278
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• 2004

In this paper, we describe our experience in the design and implementation of the SMART file system to handle multimedia workload. Our work has three design objectives: (ⅰ) efficient support for sequential workload, (ⅱ) avoiding disk fragmentation, (ⅲ) logical unit based file access. To achieve these three objectives, we develop a file system where a file consists of linked list of Data Unit Group. Instead of tree like structure of the legacy Unix file system, we use single level file structure. Our file system can also access the file based upon the logical unit which can be video frame or audio samples. Data Unit Group is a group of logical data units which is allocated continuous disk blocks. At the beginning of each Data Unit Group, there exists an index array. Each index points to the beginning of logical data units, e.g. frames in the Data Unit Group. This index array enables the random access and sequencial access of semantic data units. SMART file system is elaborately tailored to effectively support multimedia workload. We perform physical experiments and compare the performance of SMART file system with EXT2 file system and SGI XFS file system. In this experiment, SMART file system exhibits superior performance under streaming workload.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.7-16
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• 2007

In this paper, we introduce a new design environment for efficient multiprocessor system-on-chip design space exploration. The design environment takes a process network model as input system specification. The process network model has been widely used for modeling signal processing applications because of its excellent modeling power. However, it has limitation in predictability, which could cause severe problem for real time systems. This paper proposes a new approach that enables static analysis of a process network model by converting it to a hierarchical synchronous dataflow model. For efficient design space exploration in the early design step, mapping application to target architectures has been a crucial part for finding better solution. In this paper, we propose an efficient mapping algorithm. Our mapping algorithm supports both single bus architecture and multiple bus architecture. In the experiments, we show that the automatic conversion approach of the process network model for static analysis is performed successfully for several signal processing applications, and show the effectiveness of our mapping algorithm by comparing it with previous approaches.